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[src/trunk]: src/sys/arch Add support for (FDT-ized) Amlogic Meson8b.
details: https://anonhg.NetBSD.org/src/rev/3ee5856b7e95
branches: trunk
changeset: 447637:3ee5856b7e95
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Jan 19 20:56:03 2019 +0000
description:
Add support for (FDT-ized) Amlogic Meson8b.
diffstat:
sys/arch/arm/amlogic/files.meson | 77 ++
sys/arch/arm/amlogic/meson8b_clkc.c | 264 +++++++++
sys/arch/arm/amlogic/meson8b_clkc.h | 162 ++++++
sys/arch/arm/amlogic/meson8b_pinctrl.c | 532 ++++++++++++++++++++
sys/arch/arm/amlogic/meson_clk.c | 369 +++++++++++++
sys/arch/arm/amlogic/meson_clk.h | 344 ++++++++++++
sys/arch/arm/amlogic/meson_clk_div.c | 133 +++++
sys/arch/arm/amlogic/meson_clk_fixed.c | 47 +
sys/arch/arm/amlogic/meson_clk_fixed_factor.c | 103 +++
sys/arch/arm/amlogic/meson_clk_gate.c | 69 ++
sys/arch/arm/amlogic/meson_clk_mpll.c | 83 +++
sys/arch/arm/amlogic/meson_clk_mux.c | 54 ++
sys/arch/arm/amlogic/meson_clk_pll.c | 91 +++
sys/arch/arm/amlogic/meson_dwmac.c | 194 +++++++
sys/arch/arm/amlogic/meson_pinctrl.c | 566 +++++++++++++++++++++
sys/arch/arm/amlogic/meson_pinctrl.h | 81 +++
sys/arch/arm/amlogic/meson_platform.c | 370 +++++++++++++
sys/arch/arm/amlogic/meson_resets.c | 151 +++++
sys/arch/arm/amlogic/meson_rng.c | 132 ++++
sys/arch/arm/amlogic/meson_sdio.c | 690 ++++++++++++++++++++++++++
sys/arch/arm/amlogic/meson_sdioreg.h | 116 ++++
sys/arch/arm/amlogic/meson_uart.c | 505 +++++++++++++++++++
sys/arch/arm/amlogic/meson_uart.h | 57 ++
sys/arch/arm/amlogic/meson_usbphy.c | 221 ++++++++
sys/arch/arm/amlogic/meson_wdt.c | 164 ++++++
sys/arch/arm/dts/meson8b-odroidc1.dts | 30 +
sys/arch/arm/dts/meson8b.dtsi | 38 +
sys/arch/arm/fdt/a9tmr_fdt.c | 8 +-
sys/arch/arm/fdt/cpu_fdt.c | 6 +-
sys/arch/arm/fdt/l2cc_fdt.c | 7 +-
sys/arch/evbarm/conf/GENERIC | 22 +-
sys/arch/evbarm/conf/files.generic | 3 +-
32 files changed, 5678 insertions(+), 11 deletions(-)
diffs (truncated from 5972 to 300 lines):
diff -r 57ed3ea6e7e3 -r 3ee5856b7e95 sys/arch/arm/amlogic/files.meson
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/amlogic/files.meson Sat Jan 19 20:56:03 2019 +0000
@@ -0,0 +1,77 @@
+# $NetBSD: files.meson,v 1.1 2019/01/19 20:56:03 jmcneill Exp $
+#
+# Configuration info for Amlogic Meson family SoCs
+#
+#
+
+file arch/arm/amlogic/meson_platform.c soc_meson
+
+# Common clocks
+define meson_clk
+file arch/arm/amlogic/meson_clk.c meson_clk
+file arch/arm/amlogic/meson_clk_div.c meson_clk
+file arch/arm/amlogic/meson_clk_fixed.c meson_clk
+file arch/arm/amlogic/meson_clk_fixed_factor.c meson_clk
+file arch/arm/amlogic/meson_clk_gate.c meson_clk
+file arch/arm/amlogic/meson_clk_mpll.c meson_clk
+file arch/arm/amlogic/meson_clk_mux.c meson_clk
+file arch/arm/amlogic/meson_clk_pll.c meson_clk
+
+# Meson8b clock controller
+device meson8bclkc: meson_clk
+attach meson8bclkc at fdt with meson8b_clkc
+file arch/arm/amlogic/meson8b_clkc.c meson8b_clkc
+
+# Meson reset controller
+device mesonresets
+attach mesonresets at fdt with meson_resets
+file arch/arm/amlogic/meson_resets.c meson_resets
+
+# UART
+device mesonuart
+attach mesonuart at fdt with meson_uart
+file arch/arm/amlogic/meson_uart.c meson_uart
+
+# GPIO
+device mesonpinctrl: gpiobus
+attach mesonpinctrl at fdt with meson_pinctrl
+file arch/arm/amlogic/meson_pinctrl.c meson_pinctrl
+file arch/arm/amlogic/meson8b_pinctrl.c meson_pinctrl & soc_meson8b
+
+# SDHC
+#device mesonsdhc: sdmmcbus
+#attach mesonsdhc at fdt with meson_sdhc
+#file arch/arm/amlogic/meson_sdhc.c meson_sdhc
+
+# SDIO
+device mesonsdio: sdmmcbus
+attach mesonsdio at fdt with meson_sdio
+file arch/arm/amlogic/meson_sdio.c meson_sdio
+
+# USB PHY
+device mesonusbphy
+attach mesonusbphy at fdt with meson_usbphy
+file arch/arm/amlogic/meson_usbphy.c meson_usbphy
+
+# RTC
+#device mesonrtc
+#attach mesonrtc at fdt with meson_rtc
+#file arch/arm/amlogic/meson_rtc.c meson_rtc
+
+# RNG
+device mesonrng
+attach mesonrng at fdt with meson_rng
+file arch/arm/amlogic/meson_rng.c meson_rng
+
+# GMAC
+attach awge at fdt with meson_dwmac
+file arch/arm/amlogic/meson_dwmac.c meson_dwmac
+
+# Watchdog
+device mesonwdt: sysmon_wdog
+attach mesonwdt at fdt with meson_wdt
+file arch/arm/amlogic/meson_wdt.c meson_wdt
+
+# SOC parameters
+defflag opt_soc.h SOC_MESON
+defflag opt_soc.h SOC_MESON8B: SOC_MESON
diff -r 57ed3ea6e7e3 -r 3ee5856b7e95 sys/arch/arm/amlogic/meson8b_clkc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/amlogic/meson8b_clkc.c Sat Jan 19 20:56:03 2019 +0000
@@ -0,0 +1,264 @@
+/* $NetBSD: meson8b_clkc.c,v 1.1 2019/01/19 20:56:03 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2019 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: meson8b_clkc.c,v 1.1 2019/01/19 20:56:03 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/amlogic/meson_clk.h>
+#include <arm/amlogic/meson8b_clkc.h>
+
+/*
+ * The DT for amlogic,meson8b-clkc defines two reg resources. The first
+ * is not used by this driver.
+ */
+#define MESON8B_CLKC_REG_INDEX 1
+
+#define CBUS_REG(x) ((x) << 2)
+
+#define HHI_GCLK_MPEG0 CBUS_REG(0x50)
+#define HHI_GCLK_MPEG1 CBUS_REG(0x51)
+#define HHI_GCLK_MPEG2 CBUS_REG(0x52)
+#define HHI_SYS_CPU_CLK_CNTL1 CBUS_REG(0x57)
+#define HHI_MPEG_CLK_CNTL CBUS_REG(0x5d)
+#define HHI_SYS_CPU_CLK_CNTL0 CBUS_REG(0x67)
+#define HHI_MPLL_CNTL CBUS_REG(0xa0)
+#define HHI_MPLL_CNTL2 CBUS_REG(0xa1)
+#define HHI_MPLL_CNTL5 CBUS_REG(0xa4)
+#define HHI_MPLL_CNTL6 CBUS_REG(0xa5)
+#define HHI_MPLL_CNTL7 CBUS_REG(0xa6)
+#define HHI_MPLL_CNTL8 CBUS_REG(0xa7)
+#define HHI_MPLL_CNTL9 CBUS_REG(0xa8)
+#define HHI_SYS_PLL_CNTL CBUS_REG(0xc0)
+
+static int meson8b_clkc_match(device_t, cfdata_t, void *);
+static void meson8b_clkc_attach(device_t, device_t, void *);
+
+static const char * const compatible[] = {
+ "amlogic,meson8b-clkc",
+ NULL
+};
+
+CFATTACH_DECL_NEW(meson8b_clkc, sizeof(struct meson_clk_softc),
+ meson8b_clkc_match, meson8b_clkc_attach, NULL, NULL);
+
+static struct meson_clk_reset meson8b_clkc_resets[] = {
+ MESON_CLK_RESET(MESON8B_RESET_CPU0_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 24),
+ MESON_CLK_RESET(MESON8B_RESET_CPU1_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 25),
+ MESON_CLK_RESET(MESON8B_RESET_CPU2_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 26),
+ MESON_CLK_RESET(MESON8B_RESET_CPU3_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 27),
+};
+
+static const char *mpeg_sel_parents[] = { "xtal", NULL, "fclk_div7", "mpll_clkout1", "mpll_clkout2", "fclk_div4", "fclk_div3", "fclk_div5" };
+static const char *cpu_in_sel_parents[] = { "xtal", "sys_pll" };
+static const char *cpu_scale_out_sel_parents[] = { "cpu_in_sel", "cpu_in_div2", "cpu_in_div3", "cpu_scale_div" };
+static const char *cpu_clk_parents[] = { "xtal", "cpu_scale_out_sel" };
+static const char *periph_clk_sel_parents[] = { "cpu_clk_div2", "cpu_clk_div3", "cpu_clk_div4", "cpu_clk_div5", "cpu_clk_div6", "cpu_clk_div7", "cpu_clk_div8" };
+
+static struct meson_clk_clk meson8b_clkc_clks[] = {
+
+ MESON_CLK_FIXED(MESON8B_CLOCK_XTAL, "xtal", 24000000),
+
+ MESON_CLK_PLL(MESON8B_CLOCK_PLL_SYS_DCO, "pll_sys_dco", "xtal",
+ MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
+ MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
+ MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */
+ MESON_CLK_PLL_REG_INVALID, /* frac */
+ MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
+ MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
+ 0),
+
+ MESON_CLK_DIV(MESON8B_CLOCK_PLL_SYS, "sys_pll", "pll_sys_dco",
+ HHI_SYS_PLL_CNTL, /* reg */
+ __BITS(17,16), /* div */
+ MESON_CLK_DIV_POWER_OF_TWO),
+
+ MESON_CLK_MUX(MESON8B_CLOCK_CPU_IN_SEL, "cpu_in_sel", cpu_in_sel_parents,
+ HHI_SYS_CPU_CLK_CNTL0, /* reg */
+ __BIT(0), /* sel */
+ 0),
+
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_IN_DIV2, "cpu_in_div2", "cpu_in_sel", 2, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_IN_DIV3, "cpu_in_div3", "cpu_in_sel", 3, 1),
+
+ MESON_CLK_DIV(MESON8B_CLOCK_CPU_SCALE_DIV, "cpu_scale_div", "cpu_in_sel",
+ HHI_SYS_CPU_CLK_CNTL1, /* reg */
+ __BITS(29,20), /* div */
+ MESON_CLK_DIV_CPU_SCALE_TABLE),
+
+ MESON_CLK_MUX(MESON8B_CLOCK_CPU_SCALE_OUT_SEL, "cpu_scale_out_sel", cpu_scale_out_sel_parents,
+ HHI_SYS_CPU_CLK_CNTL0, /* reg */
+ __BITS(3,2), /* sel */
+ 0),
+
+ MESON_CLK_MUX(MESON8B_CLOCK_CPUCLK, "cpu_clk", cpu_clk_parents,
+ HHI_SYS_CPU_CLK_CNTL0, /* reg */
+ __BIT(7), /* sel */
+ 0),
+
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV2, "cpu_clk_div2", "cpu_clk", 2, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV3, "cpu_clk_div3", "cpu_clk", 3, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV4, "cpu_clk_div4", "cpu_clk", 4, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV5, "cpu_clk_div5", "cpu_clk", 5, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV6, "cpu_clk_div6", "cpu_clk", 6, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV7, "cpu_clk_div7", "cpu_clk", 7, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV8, "cpu_clk_div8", "cpu_clk", 8, 1),
+
+ MESON_CLK_MUX(MESON8B_CLOCK_PERIPH_SEL, "periph_clk_sel", periph_clk_sel_parents,
+ HHI_SYS_CPU_CLK_CNTL1, /* reg */
+ __BITS(8,6), /* sel */
+ 0),
+ MESON_CLK_GATE_FLAGS(MESON8B_CLOCK_PERIPH, "periph_clk_dis", "periph_clk_sel",
+ HHI_SYS_CPU_CLK_CNTL1, /* reg */
+ 17, /* bit */
+ MESON_CLK_GATE_SET_TO_DISABLE),
+
+ MESON_CLK_PLL(MESON8B_CLOCK_PLL_FIXED_DCO, "pll_fixed_dco", "xtal",
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */
+ 0),
+
+ MESON_CLK_DIV(MESON8B_CLOCK_PLL_FIXED, "pll_fixed", "pll_fixed_dco",
+ HHI_MPLL_CNTL, /* reg */
+ __BITS(17,16), /* div */
+ MESON_CLK_DIV_POWER_OF_TWO),
+
+ MESON_CLK_DIV(MESON8B_CLOCK_MPLL_PREDIV, "mpll_prediv", "pll_fixed",
+ HHI_MPLL_CNTL5, /* reg */
+ __BIT(12), /* div */
+ 0),
+
+ MESON_CLK_MPLL(MESON8B_CLOCK_MPLL0_DIV, "mpll0_div", "mpll_prediv",
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */
+ 0),
+ MESON_CLK_MPLL(MESON8B_CLOCK_MPLL1_DIV, "mpll1_div", "mpll_prediv",
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
+ MESON_CLK_PLL_REG_INVALID, /* ssen */
+ 0),
+ MESON_CLK_MPLL(MESON8B_CLOCK_MPLL2_DIV, "mpll2_div", "mpll_prediv",
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
+ MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
+ MESON_CLK_PLL_REG_INVALID, /* ssen */
+ 0),
+
+ MESON_CLK_GATE(MESON8B_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14),
+ MESON_CLK_GATE(MESON8B_CLOCK_MPLL1, "mpll1", "mpll1_div", HHI_MPLL_CNTL8, 14),
+ MESON_CLK_GATE(MESON8B_CLOCK_MPLL2, "mpll2", "mpll2_div", HHI_MPLL_CNTL9, 14),
+
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV2_DIV, "fclk_div2_div", "pll_fixed", 2, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV3_DIV, "fclk_div3_div", "pll_fixed", 3, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV4_DIV, "fclk_div4_div", "pll_fixed", 4, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV5_DIV, "fclk_div5_div", "pll_fixed", 5, 1),
+ MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV7_DIV, "fclk_div7_div", "pll_fixed", 7, 1),
+
+ MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV2, "fclk_div2", "fclk_div2_div", HHI_MPLL_CNTL6, 27),
+ MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV3, "fclk_div3", "fclk_div3_div", HHI_MPLL_CNTL6, 28),
+ MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV4, "fclk_div4", "fclk_div4_div", HHI_MPLL_CNTL6, 29),
+ MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV5, "fclk_div5", "fclk_div5_div", HHI_MPLL_CNTL6, 30),
+ MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV7, "fclk_div7", "fclk_div7_div", HHI_MPLL_CNTL6, 31),
+
+ MESON_CLK_MUX(MESON8B_CLOCK_MPEG_SEL, "mpeg_sel", mpeg_sel_parents,
+ HHI_MPEG_CLK_CNTL, /* reg */
+ __BITS(14,12), /* sel */
+ 0),
+
+ MESON_CLK_DIV(MESON8B_CLOCK_MPEG_DIV, "mpeg_div", "mpeg_sel",
+ HHI_MPEG_CLK_CNTL, /* reg */
+ __BITS(6,0), /* div */
+ 0),
+
+ MESON_CLK_GATE(MESON8B_CLOCK_CLK81, "clk81", "mpeg_div", HHI_MPEG_CLK_CNTL, 7),
+
+ MESON_CLK_GATE(MESON8B_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9),
+ MESON_CLK_GATE(MESON8B_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10),
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