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[src/trunk]: src/sys/arch/arm Start CPUs more like aarch64 by using a cpu_mpi...
details: https://anonhg.NetBSD.org/src/rev/a34a60cff3a0
branches: trunk
changeset: 447179:a34a60cff3a0
user: skrll <skrll%NetBSD.org@localhost>
date: Thu Jan 03 10:26:41 2019 +0000
description:
Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.
Towards big.LITTLE support.
diffstat:
sys/arch/arm/arm/armv6_start.S | 92 ++++++++++++++++++++++++-----------
sys/arch/arm/arm32/arm32_boot.c | 22 ++++----
sys/arch/arm/arm32/arm32_machdep.c | 17 ++++-
sys/arch/arm/arm32/cpu.c | 46 ++++++++++-------
sys/arch/arm/broadcom/bcm2835_intr.c | 18 +++---
sys/arch/arm/fdt/cpu_fdt.c | 30 +----------
sys/arch/arm/include/arm32/machdep.h | 4 +-
sys/arch/arm/include/cpu.h | 10 +++-
8 files changed, 136 insertions(+), 103 deletions(-)
diffs (truncated from 591 to 300 lines):
diff -r 7701023bfb92 -r a34a60cff3a0 sys/arch/arm/arm/armv6_start.S
--- a/sys/arch/arm/arm/armv6_start.S Thu Jan 03 10:16:43 2019 +0000
+++ b/sys/arch/arm/arm/armv6_start.S Thu Jan 03 10:26:41 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.4 2019/01/02 16:27:04 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.5 2019/01/03 10:26:41 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -160,6 +160,12 @@
#endif
#ifdef VERBOSE_INIT_ARM
+ VPRINTF("\n\rmidr :")
+ mrc p15, 0, r0, c0, c0, 0 // MIDR
+ VPRINTX(r0)
+ VPRINTF("\n\rmpidr:")
+ mrc p15, 0, r0, c0, c0, 5 // MPIDR
+ VPRINTX(r0)
VPRINTF("\n\rttb0 :")
mrc p15, 0, r0, c2, c0, 0 // TTBR0 read
VPRINTX(r0)
@@ -516,8 +522,14 @@
0)
-//
-// Perform the initialization of the an ARMv7 core required by NetBSD.
+/*
+ * Perform the initialization of the an ARMv7 core required by NetBSD.
+ *
+ * Uses the following callee saved registers:
+ *
+ * Callee saved:
+ * r4, r5, r6, r7
+ */
armv7_init:
.arch armv7a
@@ -618,6 +630,14 @@
.ltorg
+/*
+ * Transititions the CPU to using the TTB passed in r0.
+ *
+ * Uses the following callee saved registers:
+ *
+ * Callee saved:
+ * r4, r5
+ */
armv7_mmuinit:
// Because the MMU may already be on do a typical sequence to set
@@ -740,22 +760,45 @@
ldr R_TMP2, =start_stacks_top
sub sp, R_TMP2, R_VTOPDIFF
+#ifdef VERBOSE_INIT_ARM
+ VPRINTF("\n\rmidr :")
+ mrc p15, 0, r0, c0, c0, 0 // MIDR
+ VPRINTX(r0)
+ VPRINTF("\n\rmpidr:")
+ mrc p15, 0, r0, c0, c0, 5 // MPIDR
+ VPRINTX(r0)
+#endif
+
mrc p15, 0, r4, c0, c0, 5 // MPIDR get
- and r4, r4, #7 // get our cpu numder
+ and r4, #(MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0)
+
+ mov r0, #0
+ ldr r1, =cpu_mpidr
+ sub r1, R_VTOPDIFF
+1:
+ ldr r2, [r1, r0, lsl #2] // r2 = cpu_mpidr[r0]
+ cmp r2, r4
+ beq 2f // found our mpidr
- mov r5, r4
+ add r0, #1
+ cmp r0, #MAXCPUS
+ bne 1b
+
+ // Not found our mpidr in the list - use Aff0 for cpuindex
+ and r0, r4, #7
+2:
+ mov R_TMP2, r0 // save cpu_index for later
+
+ VPRINTF("index: ")
+ VPRINTX(R_TMP2)
+ XPUTC('\n')
+ XPUTC('\r')
+
+ mov r5, R_TMP2
lsl r5, #INIT_ARM_STACK_SHIFT
sub sp, sp, r5
- XPUTC('c')
- mov r0, r4
- add r0, #'0'
- bl uartputc
- XPUTC(':')
-
- mov r0, sp
- bl generic_printx
-
+ VPRINTX(sp)
XPUTC('\n')
XPUTC('\r')
@@ -776,21 +819,12 @@
* Now running with real kernel VA via bootstrap tables
*/
armv7_mpcontinuation:
- ldr R_TMP2, =start_stacks_top
-
- mrc p15, 0, r4, c0, c0, 5 // MPIDR get
- and r4, r4, #7 // get our cpu numder
-
- mov r5, r4
- lsl r5, #INIT_ARM_STACK_SHIFT
- sub sp, R_TMP2, r5
+ // Adjust stack back to KVA address
+ add sp, sp, R_VTOPDIFF
VPRINTF("go\n\r")
- mrc p15, 0, r4, c0, c0, 5 // MPIDR get
- and r4, r4, #7 // get our cpu numder
-
- mov r0, r4
+ mov r0, R_TMP2 // index into cpu_mpidr[] or cpu_number if not found
bl cpu_init_secondary_processor
/* Wait for cpu_boot_secondary_processors the when cpu_info is allocated, etc */
@@ -799,7 +833,7 @@
movt r6, #:upper16:arm_cpu_mbox
mov r5, #1 // bitmask...
- lsl r5, r4 // ... for our cpu
+ lsl r5, R_TMP2 // ... for our cpu
1: dmb // data memory barrier
ldr r2, [r6] // load mbox
@@ -809,7 +843,7 @@
movw r0, #:lower16:cpu_info
movt r0, #:upper16:cpu_info // get pointer to cpu_infos
- ldr r5, [r0, r4, lsl #2] // load our cpu_info
+ ldr r5, [r0, R_TMP2, lsl #2] // load our cpu_info
ldr r6, [r5, #CI_IDLELWP] // get the idlelwp
ldr r7, [r6, #L_PCB] // now get its pcb
ldr sp, [r7, #PCB_KSP] // finally, we can load our SP
@@ -823,7 +857,7 @@
str r6, [r5, #CI_CURLWP] // and note we are running on it
mov r0, r5 // pass cpu_info
- mov r1, r4 // pass cpu_id
+ mov r1, R_TMP2 // pass cpu_index
movw r2, #:lower16:MD_CPU_HATCH // pass md_cpu_hatch
movt r2, #:upper16:MD_CPU_HATCH // pass md_cpu_hatch
bl _C_LABEL(cpu_hatch)
diff -r 7701023bfb92 -r a34a60cff3a0 sys/arch/arm/arm32/arm32_boot.c
--- a/sys/arch/arm/arm32/arm32_boot.c Thu Jan 03 10:16:43 2019 +0000
+++ b/sys/arch/arm/arm32/arm32_boot.c Thu Jan 03 10:26:41 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_boot.c,v 1.27 2018/10/31 09:31:01 skrll Exp $ */
+/* $NetBSD: arm32_boot.c,v 1.28 2019/01/03 10:26:41 skrll Exp $ */
/*
* Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
@@ -122,7 +122,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.27 2018/10/31 09:31:01 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.28 2019/01/03 10:26:41 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_cputypes.h"
@@ -338,25 +338,25 @@
* of the idlelwp for this cpu.
*/
void
-cpu_hatch(struct cpu_info *ci, cpuid_t cpuid, void (*md_cpu_init)(struct cpu_info *))
+cpu_hatch(struct cpu_info *ci, u_int cpuindex, void (*md_cpu_init)(struct cpu_info *))
{
- KASSERT(cpu_index(ci) == cpuid);
+ KASSERT(cpu_index(ci) == cpuindex);
/*
* Raise our IPL to the max
*/
splhigh();
- VPRINTF("%s(%s): ", __func__, ci->ci_data.cpu_name);
+ VPRINTF("%s(%s): ", __func__, cpu_name(ci));
ci->ci_ctrl = armreg_sctlr_read();
uint32_t mpidr = armreg_mpidr_read();
if (mpidr & MPIDR_MT) {
- ci->ci_data.cpu_smt_id = mpidr & MPIDR_AFF0;
- ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF1;
- ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF2;
+ ci->ci_smt_id = mpidr & MPIDR_AFF0;
+ ci->ci_core_id = mpidr & MPIDR_AFF1;
+ ci->ci_package_id = mpidr & MPIDR_AFF2;
} else {
- ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF0;
- ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF1;
+ ci->ci_core_id = mpidr & MPIDR_AFF0;
+ ci->ci_package_id = mpidr & MPIDR_AFF1;
}
/*
@@ -423,7 +423,7 @@
VPRINTF(" done!\n");
/* Notify cpu_boot_secondary_processors that we're done */
- atomic_and_32(&arm_cpu_mbox, ~__BIT(cpuid));
+ atomic_and_32(&arm_cpu_mbox, ~__BIT(cpuindex));
membar_producer();
__asm __volatile("sev; sev; sev");
}
diff -r 7701023bfb92 -r a34a60cff3a0 sys/arch/arm/arm32/arm32_machdep.c
--- a/sys/arch/arm/arm32/arm32_machdep.c Thu Jan 03 10:16:43 2019 +0000
+++ b/sys/arch/arm/arm32/arm32_machdep.c Thu Jan 03 10:26:41 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_machdep.c,v 1.124 2018/10/19 08:30:57 skrll Exp $ */
+/* $NetBSD: arm32_machdep.c,v 1.125 2019/01/03 10:26:41 skrll Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.124 2018/10/19 08:30:57 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.125 2019/01/03 10:26:41 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_arm_start.h"
@@ -704,7 +704,7 @@
vaddr_t
cpu_uarea_alloc_idlelwp(struct cpu_info *ci)
{
- const vaddr_t va = idlestack.pv_va + ci->ci_cpuid * USPACE;
+ const vaddr_t va = idlestack.pv_va + cpu_index(ci) * USPACE;
// printf("%s: %s: va=%lx\n", __func__, ci->ci_data.cpu_name, va);
return va;
}
@@ -723,13 +723,15 @@
*
*/
void
-cpu_init_secondary_processor(int cpuno)
+cpu_init_secondary_processor(int cpuindex)
{
// pmap_kernel has been sucessfully built and we can switch to it
cpu_domains(DOMAIN_DEFAULT);
cpu_idcache_wbinv_all();
+ VPRINTS("index: ");
+ VPRINTX(cpuindex);
VPRINTS(" ttb");
cpu_setup(boot_args);
@@ -763,9 +765,14 @@
VPRINTS(")");
VPRINTS(" (TTBCR=");
VPRINTX(armreg_ttbcr_read());
+ VPRINTS(")");
#endif
- atomic_or_uint(&arm_cpu_hatched, __BIT(cpuno));
+ atomic_or_uint(&arm_cpu_hatched, __BIT(cpuindex));
+
+ VPRINTS(" hatched=");
+ VPRINTX(arm_cpu_hatched);
+ VPRINTS("\n\r");
/* return to assembly to Wait for cpu_boot_secondary_processors */
}
diff -r 7701023bfb92 -r a34a60cff3a0 sys/arch/arm/arm32/cpu.c
--- a/sys/arch/arm/arm32/cpu.c Thu Jan 03 10:16:43 2019 +0000
+++ b/sys/arch/arm/arm32/cpu.c Thu Jan 03 10:26:41 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.124 2019/01/02 09:04:09 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.125 2019/01/03 10:26:41 skrll Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.124 2019/01/02 09:04:09 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.125 2019/01/03 10:26:41 skrll Exp $");
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