[src/trunk]: src/sys/arch/arm/arm Whitespace

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/0168ca15a9a0
branches:  trunk
changeset: 447148:0168ca15a9a0
user:      skrll <skrll%NetBSD.org@localhost>
date:      Wed Jan 02 16:27:04 2019 +0000

description:
Whitespace

diffstat:

 sys/arch/arm/arm/armv6_start.S |  5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diffs (33 lines):

diff -r bf9a5f90d115 -r 0168ca15a9a0 sys/arch/arm/arm/armv6_start.S
--- a/sys/arch/arm/arm/armv6_start.S    Wed Jan 02 16:17:15 2019 +0000
+++ b/sys/arch/arm/arm/armv6_start.S    Wed Jan 02 16:27:04 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armv6_start.S,v 1.3 2019/01/02 16:17:15 skrll Exp $    */
+/*     $NetBSD: armv6_start.S,v 1.4 2019/01/02 16:27:04 skrll Exp $    */
 
 /*-
  * Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -480,6 +480,7 @@
 #else
 #define CPU_CONTROL_EX_BEND_SET                CPU_CONTROL_EX_BEND
 #endif
+
 #ifdef ARM32_DISABLE_ALIGNMENT_FAULTS
 #define CPU_CONTROL_AFLT_ENABLE_CLR    CPU_CONTROL_AFLT_ENABLE
 #define CPU_CONTROL_AFLT_ENABLE_SET    0
@@ -487,6 +488,7 @@
 #define CPU_CONTROL_AFLT_ENABLE_CLR    0
 #define CPU_CONTROL_AFLT_ENABLE_SET    CPU_CONTROL_AFLT_ENABLE
 #endif
+
 #ifdef ARM_MMU_EXTENDED
 #define CPU_CONTROL_XP_ENABLE_CLR      0
 #define CPU_CONTROL_XP_ENABLE_SET      CPU_CONTROL_XP_ENABLE
@@ -760,7 +762,6 @@
        // disables and clears caches
        bl      armv7_init
 
-
        movw    r0, #:lower16:TEMP_L1_TABLE
        movt    r0, #:upper16:TEMP_L1_TABLE
        sub     r0, R_VTOPDIFF