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[src/trunk]: src/sys/arch/aarch64 - add workaround for Cavium ThunderX errata...
details: https://anonhg.NetBSD.org/src/rev/40903e2ee39b
branches: trunk
changeset: 446825:40903e2ee39b
user: ryo <ryo%NetBSD.org@localhost>
date: Fri Dec 21 08:01:01 2018 +0000
description:
- add workaround for Cavium ThunderX errata 27456.
- add cpufuncs table in cpu_info. each cpu clusters may have different erratum. (e.g. big.LITTLE)
diffstat:
sys/arch/aarch64/aarch64/cpu.c | 6 ++++--
sys/arch/aarch64/aarch64/cpufunc.c | 28 ++++++++++++++++++++++++++--
sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S | 19 ++++++++++++++++++-
sys/arch/aarch64/aarch64/pmap.c | 6 +++---
sys/arch/aarch64/include/cpu.h | 7 ++++++-
sys/arch/aarch64/include/cpufunc.h | 11 ++++-------
6 files changed, 61 insertions(+), 16 deletions(-)
diffs (215 lines):
diff -r 37bff03ba553 -r 40903e2ee39b sys/arch/aarch64/aarch64/cpu.c
--- a/sys/arch/aarch64/aarch64/cpu.c Fri Dec 21 07:51:17 2018 +0000
+++ b/sys/arch/aarch64/aarch64/cpu.c Fri Dec 21 08:01:01 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.14 2018/11/28 09:16:19 ryo Exp $ */
+/* $NetBSD: cpu.c,v 1.15 2018/12/21 08:01:01 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.14 2018/11/28 09:16:19 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.15 2018/12/21 08:01:01 ryo Exp $");
#include "locators.h"
#include "opt_arm_debug.h"
@@ -163,6 +163,7 @@
}
#endif /* MULTIPROCESSOR */
+ set_cpufuncs();
fpu_attach(ci);
cpu_identify1(dv, ci);
@@ -522,6 +523,7 @@
mutex_enter(&cpu_hatch_lock);
+ set_cpufuncs();
fpu_attach(ci);
cpu_identify1(ci->ci_dev, ci);
diff -r 37bff03ba553 -r 40903e2ee39b sys/arch/aarch64/aarch64/cpufunc.c
--- a/sys/arch/aarch64/aarch64/cpufunc.c Fri Dec 21 07:51:17 2018 +0000
+++ b/sys/arch/aarch64/aarch64/cpufunc.c Fri Dec 21 08:01:01 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.4 2018/08/29 06:16:40 ryo Exp $ */
+/* $NetBSD: cpufunc.c,v 1.5 2018/12/21 08:01:01 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.4 2018/08/29 06:16:40 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.5 2018/12/21 08:01:01 ryo Exp $");
#include <sys/param.h>
#include <sys/types.h>
@@ -404,3 +404,27 @@
}
__asm __volatile ("dsb ish");
}
+
+int
+set_cpufuncs(void)
+{
+ struct cpu_info * const ci = curcpu();
+ const uint32_t midr __unused = reg_midr_el1_read();
+
+ /* install default functions */
+ ci->ci_cpufuncs.cf_set_ttbr0 = aarch64_set_ttbr0;
+
+
+ /* install core/cluster specific functions */
+#ifdef CPU_THUNDERX
+ /* Cavium erratum 27456 */
+ if ((midr == CPU_ID_THUNDERXP1d0) ||
+ (midr == CPU_ID_THUNDERXP1d1) ||
+ (midr == CPU_ID_THUNDERXP2d1) ||
+ (midr == CPU_ID_THUNDERX81XXRX)) {
+ ci->ci_cpufuncs.cf_set_ttbr0 = aarch64_set_ttbr0_thunderx;
+ }
+#endif
+
+ return 0;
+}
diff -r 37bff03ba553 -r 40903e2ee39b sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S
--- a/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S Fri Dec 21 07:51:17 2018 +0000
+++ b/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S Fri Dec 21 08:01:01 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_armv8.S,v 1.2 2018/07/23 22:51:39 ryo Exp $ */
+/* $NetBSD: cpufunc_asm_armv8.S,v 1.3 2018/12/21 08:01:01 ryo Exp $ */
/*-
* Copyright (c) 2014 Robin Randhawa
@@ -32,6 +32,7 @@
* $FreeBSD: head/sys/arm64/arm64/cpufunc_asm.S 313347 2017-02-06 17:50:09Z andrew $
*/
+#include "opt_cputypes.h"
#include "opt_multiprocessor.h"
#include <aarch64/asm.h>
@@ -163,6 +164,22 @@
ret
END(aarch64_set_ttbr0)
+#ifdef CPU_THUNDERX
+/*
+ * Cavium erratum 27456
+ * void aarch64_set_ttbr0_thunderx(uint64_t ttbr0)
+ */
+ENTRY(aarch64_set_ttbr0_thunderx)
+ dsb ish
+ msr ttbr0_el1, x0
+ isb
+ ic iallu
+ dsb nsh
+ isb
+ ret
+END(aarch64_set_ttbr0_thunderx)
+#endif /* CPU_THUNDERX */
+
/* void aarch64_tlbi_all(void) */
ENTRY(aarch64_tlbi_all)
dsb ishst
diff -r 37bff03ba553 -r 40903e2ee39b sys/arch/aarch64/aarch64/pmap.c
--- a/sys/arch/aarch64/aarch64/pmap.c Fri Dec 21 07:51:17 2018 +0000
+++ b/sys/arch/aarch64/aarch64/pmap.c Fri Dec 21 08:01:01 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.33 2018/11/01 20:34:49 maxv Exp $ */
+/* $NetBSD: pmap.c,v 1.34 2018/12/21 08:01:01 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.33 2018/11/01 20:34:49 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.34 2018/12/21 08:01:01 ryo Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -1206,7 +1206,7 @@
pm->pm_asid = l->l_proc->p_pid;
ttbr0 = ((uint64_t)pm->pm_asid << 48) | pm->pm_l0table_pa;
- aarch64_set_ttbr0(ttbr0);
+ cpu_set_ttbr0(ttbr0);
pm->pm_activated = true;
diff -r 37bff03ba553 -r 40903e2ee39b sys/arch/aarch64/include/cpu.h
--- a/sys/arch/aarch64/include/cpu.h Fri Dec 21 07:51:17 2018 +0000
+++ b/sys/arch/aarch64/include/cpu.h Fri Dec 21 08:01:01 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.12 2018/11/24 22:49:35 skrll Exp $ */
+/* $NetBSD: cpu.h,v 1.13 2018/12/21 08:01:01 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -64,6 +64,10 @@
#include <sys/device_if.h>
#include <sys/intr.h>
+struct aarch64_cpufuncs {
+ void (*cf_set_ttbr0)(uint64_t);
+};
+
struct cpu_info {
struct cpu_data ci_data;
device_t ci_dev;
@@ -98,6 +102,7 @@
struct aarch64_sysctl_cpu_id ci_id;
struct aarch64_cache_info *ci_cacheinfo;
+ struct aarch64_cpufuncs ci_cpufuncs;
} __aligned(COHERENCY_UNIT);
diff -r 37bff03ba553 -r 40903e2ee39b sys/arch/aarch64/include/cpufunc.h
--- a/sys/arch/aarch64/include/cpufunc.h Fri Dec 21 07:51:17 2018 +0000
+++ b/sys/arch/aarch64/include/cpufunc.h Fri Dec 21 08:01:01 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.h,v 1.4 2018/12/15 16:54:30 alnsn Exp $ */
+/* $NetBSD: cpufunc.h,v 1.5 2018/12/21 08:01:01 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -34,12 +34,6 @@
#include <arm/armreg.h>
#include <sys/device_if.h>
-static inline int
-set_cpufuncs(void)
-{
- return 0;
-}
-
struct aarch64_cache_unit {
u_int cache_type;
#define CACHE_TYPE_UNKNOWN 0
@@ -75,6 +69,7 @@
extern u_int aarch64_cache_prefer_mask;
extern u_int cputype; /* compat arm */
+int set_cpufuncs(void);
void aarch64_getcacheinfo(void);
void aarch64_printcacheinfo(device_t);
@@ -95,7 +90,9 @@
void aarch64_drain_writebuf(void);
/* tlb op in cpufunc_asm_armv8.S */
+#define cpu_set_ttbr0(t) curcpu()->ci_cpufuncs.cf_set_ttbr0((t))
void aarch64_set_ttbr0(uint64_t);
+void aarch64_set_ttbr0_thunderx(uint64_t);
void aarch64_tlbi_all(void); /* all ASID, all VA */
void aarch64_tlbi_by_asid(int); /* an ASID, all VA */
void aarch64_tlbi_by_va(vaddr_t); /* all ASID, a VA */
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