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[src/trunk]: src/sys/arch/arm/nvidia Support SATA on TEGRA210
details: https://anonhg.NetBSD.org/src/rev/cef621584747
branches: trunk
changeset: 446686:cef621584747
user: skrll <skrll%NetBSD.org@localhost>
date: Fri Dec 14 12:29:22 2018 +0000
description:
Support SATA on TEGRA210
Thanks to jmcneill for help with this.
diffstat:
sys/arch/arm/nvidia/tegra210_car.c | 56 ++++++++-
sys/arch/arm/nvidia/tegra210_carreg.h | 3 +-
sys/arch/arm/nvidia/tegra210_xusbpad.c | 203 +++++++++++++++++++++++++++++++-
sys/arch/arm/nvidia/tegra_ahcisata.c | 184 +++++++++++++++++++++-------
sys/arch/arm/nvidia/tegra_ahcisatareg.h | 38 +++++-
sys/arch/arm/nvidia/tegra_var.h | 4 +-
6 files changed, 428 insertions(+), 60 deletions(-)
diffs (truncated from 784 to 300 lines):
diff -r 71d4f37762fe -r cef621584747 sys/arch/arm/nvidia/tegra210_car.c
--- a/sys/arch/arm/nvidia/tegra210_car.c Fri Dec 14 12:27:22 2018 +0000
+++ b/sys/arch/arm/nvidia/tegra210_car.c Fri Dec 14 12:29:22 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_car.c,v 1.22 2018/12/12 09:55:34 skrll Exp $ */
+/* $NetBSD: tegra210_car.c,v 1.23 2018/12/14 12:29:22 skrll Exp $ */
/*-
* Copyright (c) 2015-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.22 2018/12/12 09:55:34 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.23 2018/12/14 12:29:22 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -457,6 +457,9 @@
{ "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0",
NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" };
+static const char *mux_sata_p[] =
+ { "PLL_P", NULL, "PLL_C", NULL, NULL, NULL, "CLK_M" };
+
static struct tegra_clk tegra210_car_clocks[] = {
CLK_FIXED("CLK_M", TEGRA210_REF_FREQ),
@@ -536,6 +539,13 @@
CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC,
mux_hda_p),
+ CLK_MUX("MUX_SATA_OOB",
+ CAR_CLKSRC_SATA_OOB_REG , CAR_CLKSRC_SATA_OOB_SRC,
+ mux_sata_p),
+ CLK_MUX("MUX_SATA",
+ CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC,
+ mux_sata_p),
+
CLK_DIV("DIV_UARTA", "MUX_UARTA",
CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV),
CLK_DIV("DIV_UARTB", "MUX_UARTB",
@@ -595,6 +605,11 @@
CLK_DIV("DIV_HDA", "MUX_HDA",
CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV),
+ CLK_DIV("DIV_SATA_OOB", "MUX_SATA_OOB",
+ CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV),
+ CLK_DIV("DIV_SATA", "MUX_SATA",
+ CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV),
+
CLK_GATE_SIMPLE("PLL_U_OUT1", "DIV_PLL_U_OUT1",
CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN),
CLK_GATE_SIMPLE("PLL_U_OUT2", "DIV_PLL_U_OUT2",
@@ -636,6 +651,9 @@
CLK_GATE_W("HDA2HDMI", "CLK_M", CAR_DEV_W_HDA2HDMICODEC),
CLK_GATE_V("HDA2CODEC_2X", "DIV_HDA2CODEC_2X", CAR_DEV_V_HDA2CODEC_2X),
CLK_GATE_V("HDA", "DIV_HDA", CAR_DEV_V_HDA),
+
+ CLK_GATE_V("SATA_OOB", "DIV_SATA_OOB", CAR_DEV_V_SATA_OOB),
+ CLK_GATE_V("SATA", "DIV_SATA", CAR_DEV_V_SATA),
};
struct tegra210_init_parent {
@@ -661,6 +679,8 @@
{ "CML1", NULL, 0, 0 },
{ "AFI", NULL, 0, 1 },
{ "PCIE", NULL, 0, 1 },
+ { "SATA", "PLL_P", 104000000, 0 },
+ { "SATA_OOB", "PLL_P", 204000000, 0 },
};
struct tegra210_car_rst {
@@ -1681,3 +1701,35 @@
tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG,
CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE, 0);
}
+
+void
+tegra210_car_sata_enable_hw_control(void)
+{
+ device_t dev = device_find_by_driver_unit("tegra210car", 0);
+ KASSERT(dev != NULL);
+ struct tegra210_car_softc * const sc = device_private(dev);
+ bus_space_tag_t bst = sc->sc_bst;
+ bus_space_handle_t bsh = sc->sc_bsh;
+
+ tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
+ 0,
+ CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL);
+ tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
+ CAR_SATA_PLL_CFG0_SEQ_PADPLL_SLEEP_IDDQ |
+ CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET,
+ 0);
+}
+
+void
+tegra210_car_sata_enable_hw_seq(void)
+{
+ device_t dev = device_find_by_driver_unit("tegra210car", 0);
+ KASSERT(dev != NULL);
+ struct tegra210_car_softc * const sc = device_private(dev);
+ bus_space_tag_t bst = sc->sc_bst;
+ bus_space_handle_t bsh = sc->sc_bsh;
+
+ tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
+ CAR_SATA_PLL_CFG0_SEQ_ENABLE, 0);
+}
+
diff -r 71d4f37762fe -r cef621584747 sys/arch/arm/nvidia/tegra210_carreg.h
--- a/sys/arch/arm/nvidia/tegra210_carreg.h Fri Dec 14 12:27:22 2018 +0000
+++ b/sys/arch/arm/nvidia/tegra210_carreg.h Fri Dec 14 12:29:22 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_carreg.h,v 1.8 2017/09/25 08:55:07 jmcneill Exp $ */
+/* $NetBSD: tegra210_carreg.h,v 1.9 2018/12/14 12:29:22 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -552,6 +552,7 @@
#define CAR_SATA_PLL_CFG0_SEQ_STATE __BITS(27,26)
#define CAR_SATA_PLL_CFG0_SEQ_START_STATE __BIT(25)
#define CAR_SATA_PLL_CFG0_SEQ_ENABLE __BIT(24)
+#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_SLEEP_IDDQ __BIT(13)
#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7)
#define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6)
#define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
diff -r 71d4f37762fe -r cef621584747 sys/arch/arm/nvidia/tegra210_xusbpad.c
--- a/sys/arch/arm/nvidia/tegra210_xusbpad.c Fri Dec 14 12:27:22 2018 +0000
+++ b/sys/arch/arm/nvidia/tegra210_xusbpad.c Fri Dec 14 12:29:22 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_xusbpad.c,v 1.10 2018/12/12 09:55:34 skrll Exp $ */
+/* $NetBSD: tegra210_xusbpad.c,v 1.11 2018/12/14 12:29:22 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.10 2018/12/12 09:55:34 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.11 2018/12/14 12:29:22 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -63,7 +63,7 @@
#define XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_CLAMP_EN(n) __BIT((n) * 3 + 0)
#define XUSB_PADCTL_USB3_PAD_MUX_REG 0x28
-#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE __BIT(8)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE(n) __BIT(8 + (n))
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE(n) __BIT(1 + (n))
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_REG(n) (0x84 + (n) * 0x40)
@@ -98,17 +98,25 @@
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV __BITS(27,20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_MDIV __BITS(17,16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_LOCKDET_STATUS __BIT(15)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_MODE __BITS(9,8)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_BYPASS_ENABLE __BIT(7)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREERUN_ENABLE __BIT(6)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_PWR_OVRD __BIT(4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_ENABLE __BIT(3)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_SLEEP __BITS(2,1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_IDDQ __BIT(0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG 0x364
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_CTRL __BITS(27,4)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_RESET __BIT(3)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_OVRD __BIT(2)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_DONE __BIT(1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_EN __BIT(0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_3_REG 0x368
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_3_LOCKDET_CTRL __BITS(27,4)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_3_LOCKDET_RESET __BIT(0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG 0x36c
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TCLKOUT_EN __BIT(28)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_CLKDIST_CTRL __BITS(23,20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_EN __BIT(15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_SEL __BITS(13,12)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLKBUF_EN __BIT(8)
@@ -126,6 +134,44 @@
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_10_REG 0x384
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_11_REG 0x388
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG 0x860
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_PSDIV __BITS(29,28)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_NDIV __BITS(27,20)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_MDIV __BITS(17,16)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_LOCKDET_STATUS __BIT(15)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_MODE __BITS(9,8)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_BYPASS_ENABLE __BIT(7)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREERUN_ENABLE __BIT(6)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_PWR_OVRD __BIT(4)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_ENABLE __BIT(3)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_SLEEP __BITS(2,1)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_IDDQ __BIT(0)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG 0x864
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_CTRL __BITS(27,4)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_RESET __BIT(3)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_OVRD __BIT(2)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_DONE __BIT(1)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_EN __BIT(0)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_3_REG 0x868
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_3_LOCKDET_CTRL __BITS(27,4)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_3_LOCKDET_RESET __BIT(0)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG 0x86c
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TCLKOUT_EN __BIT(28)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_CLKDIST_CTRL __BITS(23,20)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_EN __BIT(15)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_SEL __BITS(13,12)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLKBUF_EN __BIT(8)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLK_SEL __BITS(7,4)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_5_REG 0x870
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_5_DCO_CTRL __BITS(23,16)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_6_REG 0x874
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_7_REG 0x878
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG 0x87c
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_DONE __BIT(31)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_OVRD __BIT(15)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_CLK_EN __BIT(13)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_EN __BIT(12)
+
#define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_1_REG(n) (0xa60 + (n) * 0x40)
#define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_TX_TERM_CTRL __BITS(19,18)
@@ -377,6 +423,153 @@
delay(50);
}
+
+static void
+tegra210_xusbpad_uphy_enable_sata(struct tegra210_xusbpad_softc *sc)
+{
+ uint32_t val;
+ int retry;
+
+ /* UPHY PLLs */
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,
+ __SHIFTIN(0x136, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_CTRL),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_CTRL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_5_REG,
+ __SHIFTIN(0x2a, XUSB_PADCTL_UPHY_PLL_S0_CTL_5_DCO_CTRL),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_5_DCO_CTRL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_1_PWR_OVRD, 0);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_OVRD, 0);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_OVRD, 0);
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLK_SEL),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLK_SEL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_SEL),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_SEL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_EN, 0);
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_MDIV),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_MDIV);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ __SHIFTIN(0x1e, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_NDIV),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_NDIV);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_PSDIV),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_PSDIV);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_IDDQ);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_SLEEP);
+
+ delay(20);
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLKBUF_EN, 0);
+
+ /* Calibration */
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_EN, 0);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_DONE) != 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (1)\n");
+ return;
+ }
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_EN);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_DONE) == 0)
+ break;
+ }
+ if (retry == 0) {
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