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[src/trunk]: src/sys/arch Make TI compile and convert TI to generic start
details: https://anonhg.NetBSD.org/src/rev/baaeddd16b0a
branches: trunk
changeset: 446035:baaeddd16b0a
user: skrll <skrll%NetBSD.org@localhost>
date: Wed Nov 21 08:55:05 2018 +0000
description:
Make TI compile and convert TI to generic start
Compile tested only (obviously)
diffstat:
sys/arch/arm/ti/files.ti | 5 +-
sys/arch/evbarm/conf/files.ti | 5 +-
sys/arch/evbarm/conf/mk.ti | 8 +-
sys/arch/evbarm/conf/std.ti | 3 +-
sys/arch/evbarm/ti/ti_start.S | 207 ------------------------------------------
5 files changed, 10 insertions(+), 218 deletions(-)
diffs (278 lines):
diff -r 6c7e027276a2 -r baaeddd16b0a sys/arch/arm/ti/files.ti
--- a/sys/arch/arm/ti/files.ti Wed Nov 21 08:49:58 2018 +0000
+++ b/sys/arch/arm/ti/files.ti Wed Nov 21 08:55:05 2018 +0000
@@ -1,9 +1,6 @@
-# $NetBSD: files.ti,v 1.3 2018/03/17 18:34:09 ryo Exp $
+# $NetBSD: files.ti,v 1.4 2018/11/21 08:55:05 skrll Exp $
#
-include arch/arm/pic/files.pic
-include arch/arm/cortex/files.cortex
-
file arch/arm/arm32/arm32_boot.c
file arch/arm/arm32/arm32_kvminit.c
file arch/arm/arm32/arm32_reboot.c
diff -r 6c7e027276a2 -r baaeddd16b0a sys/arch/evbarm/conf/files.ti
--- a/sys/arch/evbarm/conf/files.ti Wed Nov 21 08:49:58 2018 +0000
+++ b/sys/arch/evbarm/conf/files.ti Wed Nov 21 08:55:05 2018 +0000
@@ -1,6 +1,9 @@
-# $NetBSD: files.ti,v 1.1 2017/10/26 01:16:32 jakllsch Exp $
+# $NetBSD: files.ti,v 1.2 2018/11/21 08:55:05 skrll Exp $
#
+include "arch/arm/pic/files.pic"
+include "arch/arm/cortex/files.cortex"
+
include "arch/evbarm/conf/files.fdt"
include "arch/arm/ti/files.ti"
diff -r 6c7e027276a2 -r baaeddd16b0a sys/arch/evbarm/conf/mk.ti
--- a/sys/arch/evbarm/conf/mk.ti Wed Nov 21 08:49:58 2018 +0000
+++ b/sys/arch/evbarm/conf/mk.ti Wed Nov 21 08:55:05 2018 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: mk.ti,v 1.3 2017/12/13 13:52:13 jmcneill Exp $
+# $NetBSD: mk.ti,v 1.4 2018/11/21 08:55:05 skrll Exp $
.if !empty(MACHINE_ARCH:M*eb)
EXTRA_LINKFLAGS+= --be8
@@ -7,10 +7,8 @@
CPPFLAGS+= -mcpu=cortex-a8
CPPFLAGS+= -mfpu=neon
-SYSTEM_FIRST_OBJ= ti_start.o
-SYSTEM_FIRST_SFILE= ${THISARM}/ti/ti_start.S
-
-GENASSYM_EXTRAS+= ${THISARM}/beagle/genassym.cf
+SYSTEM_FIRST_OBJ= armv6_start.o
+SYSTEM_FIRST_SFILE= ${ARM}/arm/armv6_start.S
_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
diff -r 6c7e027276a2 -r baaeddd16b0a sys/arch/evbarm/conf/std.ti
--- a/sys/arch/evbarm/conf/std.ti Wed Nov 21 08:49:58 2018 +0000
+++ b/sys/arch/evbarm/conf/std.ti Wed Nov 21 08:55:05 2018 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: std.ti,v 1.4 2018/11/21 08:49:58 skrll Exp $
+# $NetBSD: std.ti,v 1.5 2018/11/21 08:55:05 skrll Exp $
#
machine evbarm arm
@@ -18,6 +18,7 @@
options __HAVE_CPU_UAREA_ALLOC_IDLELWP
options __HAVE_FAST_SOFTINTS
options __HAVE_GENERIC_CPU_INITCLOCKS
+options __HAVE_GENERIC_START
options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
options LOADADDRESS="0x80008000"
diff -r 6c7e027276a2 -r baaeddd16b0a sys/arch/evbarm/ti/ti_start.S
--- a/sys/arch/evbarm/ti/ti_start.S Wed Nov 21 08:49:58 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,207 +0,0 @@
-/* $NetBSD: ti_start.S,v 1.3 2018/09/21 12:04:10 skrll Exp $ */
-
-/*-
- * Copyright (c) 2014, 2015 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Matt Thomas of 3am Software Foundry.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "opt_console.h"
-#include "opt_cpuoptions.h"
-#include "opt_cputypes.h"
-#include "opt_multiprocessor.h"
-#include "opt_arm_debug.h"
-#include "opt_fdt.h"
-
-#include <arm/asm.h>
-#include <arm/armreg.h>
-#include "assym.h"
-
-#include <arch/arm/ti/ti_platform.h>
-
-RCSID("$NetBSD: ti_start.S,v 1.3 2018/09/21 12:04:10 skrll Exp $")
-
-#if defined(VERBOSE_INIT_ARM) && defined(CONSADDR)
-#define XPUTC(n) mov r0, n; bl xputc
-#if KERNEL_BASE_VOFFSET == 0
-#define XPUTC2(n) mov r0, n; bl xputc
-#else
-#define XPUTC2(n) mov r0, n; blx r11
-#endif
-#ifdef __ARMEB__
-#define COM_BSWAP
-#endif
-#define COM_MULT 4
-#define XPUTC_COM 1
-#else
-#define XPUTC(n)
-#define XPUTC2(n)
-#endif
-
-#define INIT_MEMSIZE 64
-#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + INIT_MEMSIZE * L1_S_SIZE - L1_TABLE_SIZE)
-
-#define MD_CPU_HATCH _C_LABEL(arm_fdt_cpu_hatch)
-
-/*
- * Kernel start routine for TI SoCs
- * At this point, this code has been loaded into SDRAM
- * and the MMU maybe on or maybe off.
- */
-#ifdef KERNEL_BASES_EQUAL
- .text
-#else
- .section .start,"ax",%progbits
-#endif
-
- .global _C_LABEL(ti_start)
-_C_LABEL(ti_start):
-#ifdef __ARMEB__
- setend be /* force big endian */
-#endif
- mov r9, #0
-
- /* Move into supervisor mode and disable IRQs/FIQs. */
- cpsid if, #PSR_SVC32_MODE
-
- /*
- * Save any arguments passed to us.
- */
- movw r4, #:lower16:uboot_args
- movt r4, #:upper16:uboot_args
- sub r4, r4, #KERNEL_BASE_VOFFSET
-
- stmia r4, {r0-r3} // Save the arguments
-
-#ifdef FDT
- /*
- * ARM boot protocol has FDT address in r2
- */
- movw r4, #:lower16:fdt_addr_r
- movt r4, #:upper16:fdt_addr_r
- sub r4, r4, #KERNEL_BASE_VOFFSET
- str r2, [r4]
-#endif
-
- /* Add DTB PA (1MB) from r2 to MMU init table */
- movw r3, #:lower16:(L1_S_SIZE - 1) /* align DTB PA to 1M */
- movt r3, #:upper16:(L1_S_SIZE - 1)
- bic r0, r2, r3
- orr r0, r0, #1 /* 1MB mapping */
- bic r1, r2, r3
- movw r3, #:lower16:(L1_S_PROTO_armv7|L1_S_APv7_KRW|L1_S_CACHEABLE)
- movt r3, #:upper16:(L1_S_PROTO_armv7|L1_S_APv7_KRW|L1_S_CACHEABLE)
- orr r1, r1, r3
- adr r3, .Lmmu_init_table_dtb /* table entry addr */
- stmia r3, {r0-r1} /* patch table entry */
-
- /*
- * Turn on the SMP bit
- */
- bl cortex_init
-
- /*
- * Set up a preliminary mapping in the MMU to allow us to run
- * at KERNEL_BASE with caches on.
- */
- movw r0, #:lower16:TEMP_L1_TABLE
- movt r0, #:upper16:TEMP_L1_TABLE
- movw r1, #:lower16:.Lmmu_init_table
- movt r1, #:upper16:.Lmmu_init_table
- bl arm_boot_l1pt_init
- XPUTC(#'D')
-
- /*
- * Turn on the MMU, Caches, etc. Return to new enabled address space.
- */
- movw r0, #:lower16:TEMP_L1_TABLE
- movt r0, #:upper16:TEMP_L1_TABLE
-#if KERNEL_BASE_VOFFSET == 0
- bl arm_cpuinit
-#else
- /*
- * After the MMU is on, we can execute in the normal .text segment
- * so setup the lr to be in .text. Cache the address for xputc
- * before we go.
- */
-#if defined(VERBOSE_INIT_ARM)
- adr r11, xputc @ for XPUTC2
-#endif
- movw lr, #:lower16:1f
- movt lr, #:upper16:1f
- b arm_cpuinit
- .pushsection .text,"ax",%progbits
-1:
-#endif
- XPUTC2(#'Z')
-
- /*
- * Jump to start in locore.S, which in turn will call initarm and main.
- */
- b start
-
- /* NOTREACHED */
-
-#ifndef KERNEL_BASES_EQUAL
- .popsection
-#endif
-
-#include <arm/cortex/a9_mpsubr.S>
-
-.Lmmu_init_table:
- MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
- L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
-
-#if KERNEL_BASE_VOFFSET != 0
- /* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
- MMU_INIT(KERNEL_BASE - KERNEL_BASE_VOFFSET,
- KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
- L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
-#endif
-
- /* Map CORE */
- MMU_INIT(TI_CORE_VBASE, TI_CORE_PBASE,
- (TI_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
- L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
-
- /* Map CORE */
- MMU_INIT(TI_CORE_PBASE, TI_CORE_PBASE,
- (TI_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
- L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
-
- /* Map CORE */
- MMU_INIT(0xe8000000, 0x48000000,
- (0x01000000 + L1_S_SIZE - 1) / L1_S_SIZE,
- L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
-
-.Lmmu_init_table_dtb:
- /* Map DTB from bootloader (patched in later) */
- MMU_INIT(0, 0, 0, 0)
-
- /* end of table */
- MMU_INIT(0, 0, 0, 0)
-
-END(_C_LABEL(ti_start))
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