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[src/trunk]: src/sys/dev/pci Decode PCI Enhanced Allocation.
details: https://anonhg.NetBSD.org/src/rev/5e68f6e02d5f
branches: trunk
changeset: 445596:5e68f6e02d5f
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Mon Nov 05 03:51:31 2018 +0000
description:
Decode PCI Enhanced Allocation.
diffstat:
sys/dev/pci/pci_subr.c | 168 +++++++++++++++++++++++++++++++++++++++++++++++-
sys/dev/pci/pcireg.h | 50 ++++++++++++++-
2 files changed, 213 insertions(+), 5 deletions(-)
diffs (260 lines):
diff -r 16ee1afc2155 -r 5e68f6e02d5f sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Mon Nov 05 02:28:32 2018 +0000
+++ b/sys/dev/pci/pci_subr.c Mon Nov 05 03:51:31 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.206 2018/10/04 07:43:12 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.207 2018/11/05 03:51:31 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.206 2018/10/04 07:43:12 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.207 2018/11/05 03:51:31 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -2409,7 +2409,167 @@
onoff("Transaction Pending", reg, PCI_AFSR_TP);
}
-/* XXX pci_conf_print_ea_cap */
+static void
+pci_conf_print_ea_cap_prop(unsigned int prop)
+{
+
+ switch (prop) {
+ case PCI_EA_PROP_MEM_NONPREF:
+ printf("Memory Space, Non-Prefetchable\n");
+ break;
+ case PCI_EA_PROP_MEM_PREF:
+ printf("Memory Space, Prefetchable\n");
+ break;
+ case PCI_EA_PROP_IO:
+ printf("I/O Space\n");
+ break;
+ case PCI_EA_PROP_VF_MEM_NONPREF:
+ printf("Resorce for VF use, Memory Space, Non-Prefetchable\n");
+ break;
+ case PCI_EA_PROP_VF_MEM_PREF:
+ printf("Resorce for VF use, Memory Space, Prefetch\n");
+ break;
+ case PCI_EA_PROP_BB_MEM_NONPREF:
+ printf("Behind the Bridge, Memory Space, Non-Pref\n");
+ break;
+ case PCI_EA_PROP_BB_MEM_PREF:
+ printf("Behind the Bridge, Memory Space. Prefetchable\n");
+ break;
+ case PCI_EA_PROP_BB_IO:
+ printf("Behind Bridge, I/O Space\n");
+ break;
+ case PCI_EA_PROP_MEM_UNAVAIL:
+ printf("Memory Space Unavailable\n");
+ break;
+ case PCI_EA_PROP_IO_UNAVAIL:
+ printf("IO Space Unavailable\n");
+ break;
+ case PCI_EA_PROP_UNAVAIL:
+ printf("Entry Unavailable for use\n");
+ break;
+ default:
+ printf("Reserved\n");
+ break;
+ }
+}
+
+static void
+pci_conf_print_ea_cap(const pcireg_t *regs, int capoff)
+{
+ pcireg_t reg, reg2;
+ unsigned int entries, entoff, i;
+
+ printf("\n Enhanced Allocation Capability Register\n");
+
+ reg = regs[o2i(capoff + PCI_EA_CAP1)];
+ printf(" EA Num Entries register: 0x%04x\n", reg >> 16);
+ entries = __SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES);
+ printf(" EA Num Entries: %u\n", entries);
+
+ /* Type 1 only */
+ if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) {
+ reg = regs[o2i(capoff + PCI_EA_CAP2)];
+ printf(" EA Capability Second register: 0x%08x\n", reg);
+ printf(" Fixed Secondary Bus Number: %hhu\n",
+ (unsigned char)__SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY));
+ printf(" Fixed Subordinate Bus Number: %hhu\n",
+ (unsigned char)__SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE));
+ entoff = capoff + 8;
+ } else
+ entoff = capoff + 4;
+
+ for (i = 0; i < entries; i++) {
+ uint64_t base, offset;
+ bool baseis64, offsetis64;
+ unsigned int bei, entry_size;
+
+ printf(" Entry %u:\n", i);
+ /* The first DW */
+ reg = regs[o2i(entoff)];
+ printf(" The first register: 0x%08x\n", reg);
+ entry_size = __SHIFTOUT(reg, PCI_EA_ES);
+ printf(" Entry size: %u\n", entry_size);
+ printf(" BAR Equivalent Indicator: ");
+ bei = __SHIFTOUT(reg, PCI_EA_BEI);
+ switch (bei) {
+ case PCI_EA_BEI_BAR0:
+ case PCI_EA_BEI_BAR1:
+ case PCI_EA_BEI_BAR2:
+ case PCI_EA_BEI_BAR3:
+ case PCI_EA_BEI_BAR4:
+ case PCI_EA_BEI_BAR5:
+ printf("BAR %u\n", bei - PCI_EA_BEI_BAR0);
+ break;
+ case PCI_EA_BEI_BEHIND:
+ printf("Behind the function\n");
+ break;
+ case PCI_EA_BEI_NOTIND:
+ printf("Not Indicated\n");
+ break;
+ case PCI_EA_BEI_EXPROM:
+ printf("Expansion ROM\n");
+ break;
+ case PCI_EA_BEI_VFBAR0:
+ case PCI_EA_BEI_VFBAR1:
+ case PCI_EA_BEI_VFBAR2:
+ case PCI_EA_BEI_VFBAR3:
+ case PCI_EA_BEI_VFBAR4:
+ case PCI_EA_BEI_VFBAR5:
+ printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0);
+ break;
+ case PCI_EA_BEI_RESERVED:
+ default:
+ printf("Reserved\n");
+ break;
+ }
+
+ printf(" Primary Properties: ");
+ pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_PP));
+ printf(" Secondary Properties: ");
+ pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_SP));
+ onoff("Writable", reg, PCI_EA_W);
+ onoff("Enable for this entry", reg, PCI_EA_E);
+
+ if (entry_size == 0) {
+ entoff += 4;
+ continue;
+ }
+
+ /* Base addr */
+ reg = regs[o2i(entoff + 4)];
+ base = reg & PCI_EA_LOWMASK;
+ baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT;
+ printf(" Base Address Register Low: 0x%08x\n", reg);
+ if (baseis64) {
+ /* 64bit */
+ reg2 = regs[o2i(entoff + 12)];
+ printf(" Base Address Register high: 0x%08x\n",
+ reg2);
+ base |= (uint64_t)reg2 << 32;
+ }
+
+ /* Offset addr */
+ reg = regs[o2i(entoff + 8)];
+ offset = reg & PCI_EA_LOWMASK;
+ offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT;
+ printf(" Max Offset Register Low: 0x%08x\n", reg);
+ if (offsetis64) {
+ /* 64bit */
+ reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))];
+ printf(" Max Offset Register high: 0x%08x\n",
+ reg2);
+ offset |= (uint64_t)reg2 << 32;
+ }
+
+ printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64
+ "\n", base, base + offset);
+
+ entoff += 4;
+ entoff += baseis64 ? 8 : 4;
+ entoff += offsetis64 ? 8 : 4;
+ }
+}
+
/* XXX pci_conf_print_fpb_cap */
static struct {
@@ -2439,7 +2599,7 @@
{ PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap },
{ PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap },
{ PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap},
- { PCI_CAP_EA, "Enhanced Allocation", NULL },
+ { PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap },
{ PCI_CAP_FPB, "Flattening Portal Bridge", NULL }
};
diff -r 16ee1afc2155 -r 5e68f6e02d5f sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h Mon Nov 05 02:28:32 2018 +0000
+++ b/sys/dev/pci/pcireg.h Mon Nov 05 03:51:31 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.142 2018/10/03 06:46:09 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.143 2018/11/05 03:51:31 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -1866,6 +1866,54 @@
* Extended capability ID: 0x0014
* Enhanced Allocation
*/
+#define PCI_EA_CAP1 0x00 /* Capability First */
+#define PCI_EA_CAP1_NUMENTRIES __BITS(21, 16) /* Num Entries */
+#define PCI_EA_CAP2 0x04 /* Capability Second (for type1) */
+#define PCI_EA_CAP2_SECONDARY __BITS(7, 0) /* Fixed Secondary Bus No. */
+#define PCI_EA_CAP2_SUBORDINATE __BITS(15, 8) /* Fixed Subordinate Bus No. */
+
+/* Bit definitions for the first DW of each entry */
+#define PCI_EA_ES __BITS(2, 0) /* Entry Size */
+#define PCI_EA_BEI __BITS(7, 4) /* BAR Equivalent Indicator */
+#define PCI_EA_BEI_BAR0 0 /* BAR0 (10h) */
+#define PCI_EA_BEI_BAR1 1 /* BAR1 (14h) */
+#define PCI_EA_BEI_BAR2 2 /* BAR2 (18h) */
+#define PCI_EA_BEI_BAR3 3 /* BAR3 (1ch) */
+#define PCI_EA_BEI_BAR4 4 /* BAR4 (20h) */
+#define PCI_EA_BEI_BAR5 5 /* BAR5 (24h) */
+#define PCI_EA_BEI_BEHIND 6 /* Behind the function (for type1) */
+#define PCI_EA_BEI_NOTIND 7 /* Not Indicated */
+#define PCI_EA_BEI_EXPROM 8 /* Expansion ROM */
+#define PCI_EA_BEI_VFBAR0 9 /* VF BAR0 */
+#define PCI_EA_BEI_VFBAR1 10 /* VF BAR1 */
+#define PCI_EA_BEI_VFBAR2 11 /* VF BAR2 */
+#define PCI_EA_BEI_VFBAR3 12 /* VF BAR3 */
+#define PCI_EA_BEI_VFBAR4 13 /* VF BAR4 */
+#define PCI_EA_BEI_VFBAR5 14 /* VF BAR5 */
+#define PCI_EA_BEI_RESERVED 15 /* Reserved (treat as Not Indicated) */
+
+#define PCI_EA_PP __BITS(15, 8) /* Primary Properties */
+#define PCI_EA_SP __BITS(23, 16) /* Secondary Properties */
+/* PP and SP's values */
+#define PCI_EA_PROP_MEM_NONPREF 0x00 /* Memory Space, Non-Prefetchable */
+#define PCI_EA_PROP_MEM_PREF 0x01 /* Memory Space, Prefetchable */
+#define PCI_EA_PROP_IO 0x02 /* I/O Space */
+#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resorce for VF use. Mem. Non-Pref */
+#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resorce for VF use. Mem. Prefetch */
+#define PCI_EA_PROP_BB_MEM_NONPREF 0x05 /* Behind Bridge: MEM. Non-Pref */
+#define PCI_EA_PROP_BB_MEM_PREF 0x06 /* Behind Bridge: MEM. Prefetch */
+#define PCI_EA_PROP_BB_IO 0x07 /* Behind Bridge: I/O Space */
+#define PCI_EA_PROP_MEM_UNAVAIL 0xfd /* Memory Space Unavailable */
+#define PCI_EA_PROP_IO_UNAVAIL 0xfe /* IO Space Unavailable */
+#define PCI_EA_PROP_UNAVAIL 0xff /* Entry Unavailable for use */
+
+#define PCI_EA_W __BIT(30) /* Writable */
+#define PCI_EA_E __BIT(31) /* Enable for this entry */
+
+#define PCI_EA_LOWMASK __BITS(31, 2) /* Low register's mask */
+#define PCI_EA_BASEMAXOFFSET_S __BIT(1) /* Field Size */
+#define PCI_EA_BASEMAXOFFSET_64BIT __BIT(1) /* 64bit */
+#define PCI_EA_BASEMAXOFFSET_32BIT 0 /* 32bit */
/*
* Extended capability ID: 0x0015
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