[src/netbsd-8]: src/sys/arch/x86/x86 Pull up following revision(s) (requested...

[snj <snj%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/be9453e8e877
branches:  netbsd-8
changeset: 435152:be9453e8e877
user:      snj <snj%NetBSD.org@localhost>
date:      Thu Jul 26 23:23:50 2018 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #936):
        sys/arch/x86/x86/coretemp.c: revision 1.36
- Detect and set Atom's Tj(max) to 90 if it's not the 45nm D400/D500/N400
   series (90 for Diamondville and 100 for Pineview). From FreeBSD r221509.
- Reduce diff a little against FreeBSD.

diffstat:

 sys/arch/x86/x86/coretemp.c |  20 ++++++++++++--------
 1 files changed, 12 insertions(+), 8 deletions(-)

diffs (50 lines):

diff -r a46af042a77a -r be9453e8e877 sys/arch/x86/x86/coretemp.c
--- a/sys/arch/x86/x86/coretemp.c       Thu Jul 26 23:21:54 2018 +0000
+++ b/sys/arch/x86/x86/coretemp.c       Thu Jul 26 23:23:50 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: coretemp.c,v 1.35 2016/07/07 06:55:40 msaitoh Exp $ */
+/* $NetBSD: coretemp.c,v 1.35.10.1 2018/07/26 23:23:50 snj Exp $ */
 
 /*-
  * Copyright (c) 2011 The NetBSD Foundation, Inc.
@@ -61,7 +61,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.35 2016/07/07 06:55:40 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.35.10.1 2018/07/26 23:23:50 snj Exp $");
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -265,14 +265,12 @@
        model = CPUID_TO_MODEL(ci->ci_signature);
        stepping = CPUID_TO_STEPPING(ci->ci_signature);
 
+       /*
+        * Use 100C as the initial value.
+        */
        sc->sc_tjmax = 100;
 
-       /*
-        * On some Core 2 CPUs, there is an undocumented
-        * MSR that tells if Tj(max) is 100 or 85. Note
-        * that MSR_IA32_EXT_CONFIG is not safe on all CPUs.
-        */
-       if ((model == 0x0F && stepping >= 2) || (model == 0x0E)) {
+       if ((model == 0x0f && stepping >= 2) || (model == 0x0e)) {
 
                if (rdmsr_safe(MSR_IA32_EXT_CONFIG, &msr) == EFAULT)
                        return;
@@ -285,6 +283,12 @@
                /* The mobile Penryn family. */
                sc->sc_tjmax = 105;
                return;
+       } else if (model == 0x1c) {
+               if (stepping == 0x0a) {
+                       /* 45nm Atom D400, N400 and D500 series */
+                       sc->sc_tjmax = 100;
+               } else
+                       sc->sc_tjmax = 90;
        } else {
                /*
                 * Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET,