Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/netbsd-8]: src/sys/dev/pci Pull up following revision(s) (requested by m...
details: https://anonhg.NetBSD.org/src/rev/fe9a04917146
branches: netbsd-8
changeset: 435148:fe9a04917146
user: snj <snj%NetBSD.org@localhost>
date: Thu Jul 26 23:11:59 2018 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #933):
sys/dev/pci/pci_subr.c: revision 1.202
sys/dev/pci/pcireg.h: revision 1.139
sys/dev/pci/ppbreg.h: revision 1.9
VGA 16 bit decode bit is not bit 3 but bit 4.
--
- Print Power Management Control/status register in 32bit.
- Simplify.
diffstat:
sys/dev/pci/pci_subr.c | 20 +++++++++-----------
sys/dev/pci/pcireg.h | 4 ++--
sys/dev/pci/ppbreg.h | 4 ++--
3 files changed, 13 insertions(+), 15 deletions(-)
diffs (93 lines):
diff -r 15856f176c59 -r fe9a04917146 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Thu Jul 26 21:41:19 2018 +0000
+++ b/sys/dev/pci/pci_subr.c Thu Jul 26 23:11:59 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.183.2.5 2018/07/26 21:07:19 snj Exp $ */
+/* $NetBSD: pci_subr.c,v 1.183.2.6 2018/07/26 23:11:59 snj Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.5 2018/07/26 21:07:19 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.6 2018/07/26 23:11:59 snj Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -1172,11 +1172,9 @@
pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
{
uint16_t caps, pmcsr;
- pcireg_t reg;
caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT;
- reg = regs[o2i(capoff + PCI_PMCSR)];
- pmcsr = reg & 0xffff;
+ pmcsr = regs[o2i(capoff + PCI_PMCSR)];
printf("\n PCI Power Management Capabilities Register\n");
@@ -1195,7 +1193,7 @@
onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT);
onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD);
- printf(" Control/status register: 0x%04x\n", pmcsr);
+ printf(" Control/status register: 0x%08x\n", pmcsr);
printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK);
onoff("PCI Express reserved", (pmcsr >> 2), 1);
onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST);
@@ -1207,11 +1205,11 @@
__SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK));
onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS);
printf(" Bridge Support Extensions register: 0x%02x\n",
- (reg >> 16) & 0xff);
- onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT);
- onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN);
- printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA));
-
+ (pmcsr >> 16) & 0xff);
+ onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT);
+ onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN);
+ printf(" Data register: 0x%02x\n",
+ __SHIFTOUT(pmcsr, PCI_PMCSR_DATA));
}
/* XXX pci_conf_print_vpd_cap */
diff -r 15856f176c59 -r fe9a04917146 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h Thu Jul 26 21:41:19 2018 +0000
+++ b/sys/dev/pci/pcireg.h Thu Jul 26 23:11:59 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.130.2.4 2018/07/26 21:07:19 snj Exp $ */
+/* $NetBSD: pcireg.h,v 1.130.2.5 2018/07/26 23:11:59 snj Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -1327,7 +1327,7 @@
#define PCI_BRIDGE_CONTROL_SERR (1 << 1)
#define PCI_BRIDGE_CONTROL_ISA (1 << 2)
#define PCI_BRIDGE_CONTROL_VGA (1 << 3)
-#define PCI_BRIDGE_CONTROL_VGA16 (1 << 3)
+#define PCI_BRIDGE_CONTROL_VGA16 (1 << 4)
#define PCI_BRIDGE_CONTROL_MABRT (1 << 5)
#define PCI_BRIDGE_CONTROL_SECBR (1 << 6)
#define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7)
diff -r 15856f176c59 -r fe9a04917146 sys/dev/pci/ppbreg.h
--- a/sys/dev/pci/ppbreg.h Thu Jul 26 21:41:19 2018 +0000
+++ b/sys/dev/pci/ppbreg.h Thu Jul 26 23:11:59 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ppbreg.h,v 1.7.2.1 2018/02/26 00:56:29 snj Exp $ */
+/* $NetBSD: ppbreg.h,v 1.7.2.2 2018/07/26 23:11:59 snj Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -100,7 +100,7 @@
#define PPB_BC_SERR_ENABLE (1U << (1 + PPB_BC_BITBASE))
#define PPB_BC_ISA_ENABLE (1U << (2 + PPB_BC_BITBASE))
#define PPB_BC_VGA_ENABLE (1U << (3 + PPB_BC_BITBASE))
-#define PPB_BC_VGA16_ENABLE (1U << (3 + PPB_BC_BITBASE))
+#define PPB_BC_VGA16_ENABLE (1U << (4 + PPB_BC_BITBASE))
#define PPB_BC_MASTER_ABORT_MODE (1U << (5 + PPB_BC_BITBASE))
#define PPB_BC_SECONDARY_RESET (1U << (6 + PPB_BC_BITBASE))
#define PPB_BC_FAST_B2B_ENABLE (1U << (7 + PPB_BC_BITBASE))
Home |
Main Index |
Thread Index |
Old Index