[src/netbsd-8]: src/sys/dev/pci Pull up following revision(s) (requested by m...

[snj <snj%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b550bc09d5a3
branches:  netbsd-8
changeset: 434671:b550bc09d5a3
user:      snj <snj%NetBSD.org@localhost>
date:      Mon Feb 26 00:56:29 2018 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #576):
        sys/dev/pci/pci_subr.c: 1.197-1.200
        sys/dev/pci/pcireg.h: 1.136-1.137
        sys/dev/pci/ppbreg.h: 1.8
 Add VGA 16bit decode bit into the PCI bridge control register. This bit is
defined in PCI-to-PCI Bridge Architecture Specification Revision 1.2. This
bit has meaning if the VGA enable bit or the VGA Palette Snoop Enable bit is
set.
 NOTE: sys/arch/x86/pci/pci_ranges.c::mmio_range_extend_by_vga_enable() and/or
some other functions should be modified.
 "s/above 300W/greater than 300W/" in pci_conf_print_pcie_power(). From
PCIe Base Spec 3.1a Errata 2017-12-13.
Cleanup:
- Don't pass a capability pointer as a argument of pci_conf_find_cap() and
  determine the first pointer in the pci_conf_find_cap() function.
- Don't pass a capability pointer as a argument of pci_conf_find_extcap()
  because it's not used.
- Remove unsed code.
- Add PCie Link Activation ECN.
- Use macro.
- KNF.

diffstat:

 sys/dev/pci/pci_subr.c |  138 ++++++++++++++++++++++++++++++------------------
 sys/dev/pci/pcireg.h   |    9 ++-
 sys/dev/pci/ppbreg.h   |    3 +-
 3 files changed, 94 insertions(+), 56 deletions(-)

diffs (truncated from 517 to 300 lines):

diff -r 2e54d995041a -r b550bc09d5a3 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c    Mon Feb 26 00:49:48 2018 +0000
+++ b/sys/dev/pci/pci_subr.c    Mon Feb 26 00:56:29 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pci_subr.c,v 1.183.2.3 2017/11/22 14:38:47 martin Exp $        */
+/*     $NetBSD: pci_subr.c,v 1.183.2.4 2018/02/26 00:56:29 snj Exp $   */
 
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
@@ -40,7 +40,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.3 2017/11/22 14:38:47 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.4 2018/02/26 00:56:29 snj Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
@@ -70,7 +70,8 @@
 #include <dev/pci/pcidevs_data.h>
 #endif
 
-static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *);
+static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *);
+static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *);
 static void pci_conf_print_pcie_power(uint8_t, unsigned int);
 
 /*
@@ -831,8 +832,7 @@
                int pcie_capoff;
                pcireg_t reg;
 
-               if (pci_conf_find_cap(regs, PCI_CAPLISTPTR_REG,
-                   PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
+               if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
                        reg = regs[o2i(pcie_capoff + PCIE_XCAP)];
                        if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC)
                                subclass = PCI_SUBCLASS_SYSTEM_RCEC;
@@ -1769,10 +1769,10 @@
        /* Capability Register */
        reg = regs[o2i(capoff)];
        printf("    Capability register: 0x%04x\n", reg >> 16);
-       pciever = (unsigned int)((reg & 0x000f0000) >> 16);
+       pciever = (unsigned int)(PCIE_XCAP_VER(reg));
        printf("      Capability version: %u\n", pciever);
        printf("      Device type: ");
-       switch ((reg & 0x00f00000) >> 20) {
+       switch (PCIE_XCAP_TYPE(reg)) {
        case PCIE_XCAP_TYPE_PCIE_DEV:   /* 0x0 */
                printf("PCI Express Endpoint device\n");
                check_upstreamport = true;
@@ -2446,13 +2446,29 @@
 };
 
 static int
-pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid,
-    int *offsetp)
+pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp)
 {
        pcireg_t rval;
+       unsigned int capptr;
        int off;
 
-       for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
+       if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT))
+               return 0;
+
+       /* Determine the Capability List Pointer register to start with. */
+       switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) {
+       case 0: /* standard device header */
+       case 1: /* PCI-PCI bridge header */
+               capptr = PCI_CAPLISTPTR_REG;
+               break;
+       case 2: /* PCI-CardBus Bridge header */
+               capptr = PCI_CARDBUS_CAPLISTPTR_REG;
+               break;
+       default:
+               return 0;
+       }
+       
+       for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]);
             off != 0; off = PCI_CAPLIST_NEXT(rval)) {
                rval = regs[o2i(off)];
                if (capid == PCI_CAPLIST_CAP(rval)) {
@@ -2511,13 +2527,6 @@
                 * the same. This is required because some capabilities
                 * appear multiple times (e.g. HyperTransport capability).
                 */
-#if 0
-               if (pci_conf_find_cap(regs, capoff, i, &off)) {
-                       rval = regs[o2i(off)];
-                       if (pci_captab[i].printfunc != NULL)
-                               pci_captab[i].printfunc(regs, off);
-               }
-#else
                for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
                     off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
                        rval = regs[o2i(off)];
@@ -2525,7 +2534,6 @@
                            && (pci_captab[i].printfunc != NULL))
                                pci_captab[i].printfunc(regs, off);
                }
-#endif
        }
 }
 
@@ -2633,14 +2641,14 @@
 }
 
 static void
-pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg;
        int pcie_capoff;
        int pcie_devtype = -1;
        bool tlp_prefix_log = false;
 
-       if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
+       if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
                reg = regs[o2i(pcie_capoff)];
                pcie_devtype = PCIE_XCAP_TYPE(reg);
                /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */
@@ -2727,7 +2735,7 @@
 }
 
 static void
-pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg, n;
        int parbtab, parbsize;
@@ -2856,7 +2864,7 @@
                        s = "275W < x <= 300W";
                        break;
                default:
-                       s = "reserved for above 300W";
+                       s = "reserved for greater than 300W";
                        break;
                }
                printf("%s\n", s);
@@ -2918,7 +2926,7 @@
 }
 
 static void
-pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg;
 
@@ -2967,7 +2975,7 @@
 }
 
 static void
-pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg;
        unsigned char nent, linktype;
@@ -3046,7 +3054,7 @@
 /* XXX pci_conf_print_rclink_ctl_cap */
 
 static void
-pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg;
 
@@ -3064,7 +3072,7 @@
 /* XXX pci_conf_print_cac_cap */
 
 static void
-pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg, cap, ctl;
        unsigned int size, i;
@@ -3107,7 +3115,7 @@
 }
 
 static void
-pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg, cap, ctl;
 
@@ -3129,7 +3137,7 @@
 }
 
 static void
-pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg, cap, ctl;
        unsigned int num;
@@ -3154,7 +3162,7 @@
 }
 
 static void
-pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t lo, hi;
 
@@ -3168,7 +3176,7 @@
 }
 
 static void
-pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff)
 {
        char buf[sizeof("99999 MB")];
        pcireg_t reg;
@@ -3280,7 +3288,7 @@
 /* XXX pci_conf_print_mriov_cap */
 
 static void
-pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg, cap, ctl;
        pcireg_t regl, regh;
@@ -3348,7 +3356,7 @@
 }
 
 static void
-pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg, ctl, sta;
 
@@ -3379,7 +3387,7 @@
 #define MEM_PBUFSIZE   sizeof("999GB")
 
 static void
-pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t cap, ctl;
        unsigned int bars, i, n;
@@ -3436,7 +3444,7 @@
 }
 
 static void
-pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg;
        unsigned int substmax, i;
@@ -3516,7 +3524,7 @@
 }
 
 static void
-pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg;
        int size, i, j;
@@ -3587,7 +3595,7 @@
 }
 
 static void
-pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg;
 
@@ -3604,7 +3612,7 @@
 }
 
 static void
-pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff)
 {
        int pcie_capoff;
        pcireg_t reg;
@@ -3626,7 +3634,7 @@
        printf("    Lane Error Status register: 0x%08x\n", reg);
 
        /* Get Max Link Width */
-       if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){
+       if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
                reg = regs[o2i(pcie_capoff + PCIE_LCAP)];
                maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);
        } else {
@@ -3657,7 +3665,7 @@
 /* XXX pci_conf_print_pmux_cap */
 
 static void
-pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff)
 {
        pcireg_t reg, cap, ctl;
        unsigned int num;
@@ -3680,7 +3688,7 @@
 }
 
 static void
-pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff)
+pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff)