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[src/netbsd-8]: src/sys/dev/mii Pull up following revision(s) (requested by m...



details:   https://anonhg.NetBSD.org/src/rev/69c74230e7a4
branches:  netbsd-8
changeset: 434402:69c74230e7a4
user:      martin <martin%NetBSD.org@localhost>
date:      Tue Nov 21 14:43:17 2017 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #363):
        sys/dev/mii/mdio.h: revision 1.4
        sys/dev/mii/mdio.h: revision 1.5
        sys/dev/mii/mdio.h: revision 1.6
        sys/dev/mii/mdio.h: revision 1.7
  Add missing RCS Id.
Fix typo.
- Update IEEE 802.3 Clause 45 definitions from IEEE 802.3 2009 to IEEE 802.3
   2015.
- Modify register names.
- Modify comments.
  Define bit definitions of MDIO_PMAPMD_CTRL1 and MDIO_AN_CTRL1.

diffstat:

 sys/dev/mii/mdio.h |  362 +++++++++++++++++++++++++++++++++++++---------------
 1 files changed, 257 insertions(+), 105 deletions(-)

diffs (truncated from 537 to 300 lines):

diff -r 2065a787348e -r 69c74230e7a4 sys/dev/mii/mdio.h
--- a/sys/dev/mii/mdio.h        Tue Nov 21 14:16:38 2017 +0000
+++ b/sys/dev/mii/mdio.h        Tue Nov 21 14:43:17 2017 +0000
@@ -1,3 +1,5 @@
+/*     $NetBSD: mdio.h,v 1.3.32.1 2017/11/21 14:43:17 martin Exp $     */
+
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -33,14 +35,13 @@
 /*
  * IEEE 802.3 Clause 45 definitions.
  * From:
- *     IEEE 802.3 2009
+ *     IEEE 802.3 2015
  *     IEEE 802.3at
  *     IEEE 802.3av
- *     IEEE 802.3az
  */
 
 /*
- * MDIO Manageable Device addresses.
+ * MDIO Manageable Device (MMD) addresses.
  * Table 45-1
  */
 #define        MDIO_MMD_PMAPMD         1
@@ -50,15 +51,37 @@
 #define        MDIO_MMD_DTEXS          5
 #define        MDIO_MMD_TC             6
 #define        MDIO_MMD_AN             7
+#define        MDIO_MMD_SEPPMA1        8
+#define        MDIO_MMD_SEPPMA2        9
+#define        MDIO_MMD_SEPPMA3        10
+#define        MDIO_MMD_SEPPMA4        11
 #define        MDIO_MMD_CL22EXT        29
 #define        MDIO_MMD_VNDSP1         30
 #define        MDIO_MMD_VNDSP2         31
 
 /*
- * MDIO PMA/PMD registers.
+ * PMA/PMD registers.
  * Table 45-3
  */
 #define MDIO_PMAPMD_CTRL1              0   /* PMA/PMD control 1 */
+#define PMAPMD_CTRL1_RESET     0x8000          /* Reset */
+#define PMAPMD_CTRL1_SPEED0    0x2000          /* Speed selection (LSB) */
+#define PMAPMD_CTRL1_LOWPWR    0x0800          /* Low power */
+#define PMAPMD_CTRL1_SPEED1    0x0040          /* Speed selection (MSB) */
+#define PMAPMD_CTRL1_SPEED2    0x003c          /* Speed selection (over 1G) */
+#define PMAPMD_CTRL1_LOOP_REM  0x0002          /* PMA remote loopback */
+#define PMAPMD_CTRL1_LOOP_LOC  0x0001          /* PMA local loopback */
+#define PMAPMD_CTRL1_SPEED_SEL52 (PMAPMD_CTRL1_SPEED0 | PMAPMD_CTRL1_SPEED1)
+#define PMAPMD_CTRL1_SPEED_MASK        (PMAPMD_CTRL1_SPEED_SEL52 \
+           | PMAPMD_CTRL1_SPEED2)
+#define PMAPMD_CTRL1_SPEED_10     0
+#define PMAPMD_CTRL1_SPEED_100    PMAPMD_CTRL1_SPEED0
+#define PMAPMD_CTRL1_SPEED_1G     PMAPMD_CTRL1_SPEED1
+#define PMAPMD_CTRL1_SPEED_10G     PMAPMD_CTRL1_SPEED_SEL52
+#define PMAPMD_CTRL1_SPEED_10PASS (PMAPMD_CTRL1_SPEED_SEL52 | (1 << 2))
+#define PMAPMD_CTRL1_SPEED_40G   (PMAPMD_CTRL1_SPEED_SEL52 | (2 << 2))
+#define PMAPMD_CTRL1_SPEED_100G   (PMAPMD_CTRL1_SPEED_SEL52 | (3 << 2))
+
 #define MDIO_PMAPMD_STAT1              1   /* PMA/PMD status 1 */
 #define MDIO_PMAPMD_DEVID1             2   /* PMA/PMD device identifier 1 */
 #define MDIO_PMAPMD_DEVID2             3   /* PMA/PMD device identifier 2 */
@@ -71,10 +94,11 @@
 #define MDIO_PMAPMD_RXSIGDTCT          10  /* 10G PMD receive signal detect */
 #define MDIO_PMAPMD_EXTABLTY           11  /* 10G PMA/PMD ext. ability reg */
 #define MDIO_PMAPMD_P2MPABLTY          12  /* P2MP ability register(802.3av)*/
-       /* Value 13 is reserved */
+#define MDIO_PMAPMD_40G100GEXTABLTY    13  /* 40G/100G extended ability */
 #define MDIO_PMAPMD_PKGID1             14  /* PMA/PMD package identifier 1 */
 #define MDIO_PMAPMD_PKGID2             15  /* PMA/PMD package identifier 2 */
-       /* Values 16 to 29 are reserved */
+#define        MDIO_PMAPMD_EEECAP              16  /* PMA/PMD EEE capability */
+       /* Values 17 to 29 are reserved */
 #define MDIO_PMAPMD_10P2BCTRL          30  /* 10P/2B PMA/PMD control */
 #define MDIO_PMAPMD_10P2BSTAT          31  /* 10P/2B PMA/PMD status */
 #define MDIO_PMAPMD_10P2BLPCTRL                32  /* 10P/2B link partner PMA/D ctrl*/
@@ -100,7 +124,7 @@
 #define MDIO_PMAPMD_10PDSRSCONF                53  /* 10P downstream ReedSolomon cnf*/
 #define MDIO_PMAPMD_10PUSDR1           54  /* 10P upstream data rate cnf1 */
 #define MDIO_PMAPMD_10PUSDR2           55  /* 10P upstream data rate cnf2 */
-#define MDIO_PMAPMD_10PUSRSCONF                56  /* 10P upnstream ReedSolomon cnf */
+#define MDIO_PMAPMD_10PUSRSCONF                56  /* 10P upstream ReedSolomon cnf */
 #define MDIO_PMAPMD_10PTONEGROUP1      57  /* 10P tone group 1 */
 #define MDIO_PMAPMD_10PTONEGROUP2      58  /* 10P tone group 2 */
 #define MDIO_PMAPMD_10PTONEPARAM1      59  /* 10P tone parameter 1 */
@@ -168,28 +192,114 @@
 #define MDIO_PMAPMD_10GTSKEWDLY2       146 /* 10G-T skew delay 2 */
 #define MDIO_PMAPMD_10GTFSTRETSTATCTRL 147 /* 10G-T fast retrain stat&ctrl */
        /* Values 148 to 149 are reserved */
-#define MDIO_PMAPMD_10GKRPMDCTRL       150 /* 10G-KR PMD control */
-#define MDIO_PMAPMD_10GKRPMDSTAT       151 /* 10G-KR PMD status */
-#define MDIO_PMAPMD_10GKRLPCOEFUPD     152 /* 10G-KR LP coefficient update */
-#define MDIO_PMAPMD_10GKRLPSTATRPT     153 /* 10G-KR LP status report */
-#define MDIO_PMAPMD_10GKRLDCOEFFUPD    154 /* 10G-KR LD coefficient update */
-#define MDIO_PMAPMD_10GKRLDSTATRPT     155 /* 10G-KR LD status report */
-       /* Values 156 to 159 are reserved */
-#define MDIO_PMAPMD_10GKXCTRL          160 /* 10G-KX control */
-#define MDIO_PMAPMD_10GKXSTAT          161 /* 10G-KX status */
-       /* Values 162 to 169 are reserved */
-#define MDIO_PMAPMD_10GRFECABLTY       170 /* 10G-R FEC ability */
-#define MDIO_PMAPMD_10GRFECCTRL                171 /* 10G-R FEC control */
-#define MDIO_PMAPMD_10GRFECCOBLCNT1    172 /* 10G-R FEC corrected blks cnt1 */
-#define MDIO_PMAPMD_10GRFECCOBLCNT2    173 /* 10G-R FEC corrected blks cnt2 */
-#define MDIO_PMAPMD_10GRFECUNCOBLCNT1  174 /* 10G-R FEC uncorrect blks cnt1 */
-#define MDIO_PMAPMD_10GRFECUNCOBLCNT2  175 /* 10G-R FEC uncorrect blks cnt2 */
-       /* Values 176 to 32767 are reserved */
+#define MDIO_PMAPMD_BASERPMDCTRL       150 /* BASE-R PMD control */
+#define MDIO_PMAPMD_BASERPMDSTAT       151 /* BASE-R PMD status */
+#define MDIO_PMAPMD_BASERLPCOEFUPDL0   152 /* BASE-R LP coeffici. update ln0*/
+#define MDIO_PMAPMD_BASERLPSTATRPTL0   153 /* BASE-R LP status report lane0 */
+#define MDIO_PMAPMD_BASERLDCOEFFUPDL0  154 /* BASE-R LD coeffici. update ln0*/
+#define MDIO_PMAPMD_BASERLDSTATRPTL0   155 /* BASE-R LD status report lane0 */
+#define MDIO_PMAPMD_BASERSTAT2         156 /* BASE-R PMD status 2 */
+#define MDIO_PMAPMD_BASERSTAT3         157 /* BASE-R PMD status 3 */
+       /* Values 158 to 159 are reserved */
+#define MDIO_PMAPMD_1000KXCTRL         160 /* 1000BASE-KX control */
+#define MDIO_PMAPMD_1000KXSTAT         161 /* 1000BASE-KX status */
+#define MDIO_PMAPMD_PMAOVHDCTRL1       162 /* PMA Overhead Control 1 */
+#define MDIO_PMAPMD_PMAOVHDCTRL2       163 /* PMA Overhead Control 2 */
+#define MDIO_PMAPMD_PMAOVHDCTRL3       164 /* PMA Overhead Control 3 */
+#define MDIO_PMAPMD_PMAOVHDSTAT1       165 /* PMA Overhead Status 1 */
+#define MDIO_PMAPMD_PMAOVHDSTAT2       166 /* PMA Overhead Status 2 */
+       /* Values 167 to 169 are reserved */
+#define MDIO_PMAPMD_BASERFECABLTY      170 /* BASE-R FEC ability */
+#define MDIO_PMAPMD_BASERFECCTRL       171 /* BASE-R FEC control */
+#define MDIO_PMAPMD_10GRFECCOBLCNTL    172 /* 10G-R FEC corrected blks cntL */
+#define MDIO_PMAPMD_10GRFECCOBLCNTH    173 /* 10G-R FEC corrected blks cntH */
+#define MDIO_PMAPMD_10GRFECUNCOBLCNTL  174 /* 10G-R FEC uncorrect blks cntL */
+#define MDIO_PMAPMD_10GRFECUNCOBLCNTH  175 /* 10G-R FEC uncorrect blks cntH */
+       /* Values 176 to 178 are reserved */
+#define MDIO_PMAPMD_CAUI4C2MRECCTLE    179 /* CAUI-4 Chip2Mod recomme. CTLE */
+#define MDIO_PMAPMD_CAUI4C2CTERDIL0    180 /* CAUI-4 Ch2Ch TxEq RxDir lane0 */
+#define MDIO_PMAPMD_CAUI4C2CTERDIL1    181 /* lane1 */
+#define MDIO_PMAPMD_CAUI4C2CTERDIL2    182 /* lane2 */
+#define MDIO_PMAPMD_CAUI4C2CTERDIL3    183 /* lane3 */
+#define MDIO_PMAPMD_CAUI4C2CTETDEL0    184 /* CAUI-4 Ch2Ch TxEq TxDet lane0 */
+#define MDIO_PMAPMD_CAUI4C2CTETDEL1    185 /* lane1 */
+#define MDIO_PMAPMD_CAUI4C2CTETDEL2    186 /* lane2 */
+#define MDIO_PMAPMD_CAUI4C2CTETDEL3    187 /* lane3 */
+       /* Values 188 to 199 are reserved */
+#define MDIO_PMAPMD_RSFECCTRL          200 /* RS-FEC Control */
+#define MDIO_PMAPMD_RSFECSTAT          201 /* RS-FEC Status */
+#define MDIO_PMAPMD_RSFECCORRCWCNTL    202 /* RS-FEC correct. codeword cntL */
+#define MDIO_PMAPMD_RSFECCORRCWCNTH    203 /* RS-FEC correct. codeword cntH */
+#define MDIO_PMAPMD_RSFECUNCORRCWCNTL  204 /* RS-FEC uncorre. codeword cntL */
+#define MDIO_PMAPMD_RSFECUNCORRCWCNTH  205 /* RS-FEC uncorre. codeword cntH */
+#define MDIO_PMAPMD_RSFECLANEMAP       206 /* RS-FEC Lane Mapping */
+       /* Values 207 to 209 are reserved */
+#define MDIO_PMAPMD_RSFECSMBLERRCNTL(x)            /* RS-FEC Symbol Error CntLow */ \
+                                       (210 + ((x) * 2)) /* lane 0 to 3 */
+#define MDIO_PMAPMD_RSFECSMBLERRCNTH(x)            /* RS-FEC Symbol Error CntHigh */ \
+                                       (211 + ((x) * 2)) /* lane 0 to 3 */
+       /* Values 218 to 229 are reserved */
+#define MDIO_PMAPMD_RSFECBIPERRCNT(x)      /* RS-FEC BIP Error Counter */ \
+                                       (230 + (x)) /* lane 0 to 19 */
+#define MDIO_PMAPMD_RSFECPCSLMAP(x)        /* RS-FEC PCS Lane Mapping */ \
+                                       (250 + (x)) /* lane 0 to 19 */
+       /* Values 270 to 279 are reserved */
+#define MDIO_PMAPMD_RSFECPCSALGNSTAT1  280 /* RS-FEC PCS Alignment Status 1 */
+#define MDIO_PMAPMD_RSFECPCSALGNSTAT2  281 /* RS-FEC PCS Alignment Status 2 */
+#define MDIO_PMAPMD_RSFECPCSALGNSTAT3  282 /* RS-FEC PCS Alignment Status 3 */
+#define MDIO_PMAPMD_RSFECPCSALGNSTAT4  283 /* RS-FEC PCS Alignment Status 4 */
+       /* Values 284 to 299 are reserved */
+#define MDIO_PMAPMD_BASERFECCORBLKCNTL(x)    /* BASE-R FEC Corr. Blk. CntL */ \
+                                       (300 + ((x) * 2)) /* lane0 to 19 */
+#define MDIO_PMAPMD_BASERFECCORBLKCNTH(x)    /* BASE-R FEC Corr. Blk. CntH */ \
+                                       (301 + ((x) * 2)) /* lane0 to 19 */
+       /* Values 340 to 699 are reserved */
+#define MDIO_PMAPMD_BASERFECUNCORBLKCNTL(x) /* BASE-R FEC UnCorr. Blk. CntL*/ \
+                                       (700 + ((x) * 2)) /* lane0 to 19 */
+#define MDIO_PMAPMD_BASERFECUNCORBLKCNTH(x) /* BASE-R FEC UnCorr. Blk. CntH*/ \
+                                       (701 + ((x) * 2)) /* lane0 to 19 */
+       /* Values 740 to 1099 are reserved */
+#define MDIO_PMAPMD_BASERLPCOEFUPD(x)      /* BASE-R LP coefficient update */\
+                                       (1100 + (x)) /* lane0 to 9 */
+       /* Values 1110 to 1199 are reserved */
+#define MDIO_PMAPMD_BASERLPSTATRPT(x)      /* BASE-R LP status report */ \
+                                       (1200 + (x)) /* lane0 to 9 */
+       /* Values 1210 to 1299 are reserved */
+#define MDIO_PMAPMD_BASERLDCOEFUPD(x)      /* BASE-R LD coefficient update */\
+                                       (1300 + (x)) /* lane0 to 9 */
+       /* Values 1310 to 1399 are reserved */
+#define MDIO_PMAPMD_BASERLDSTATRPT(x)      /* BASE-R LD status report */ \
+                                       (1400 + (x)) /* lane0 to 9 */
+       /* Values 1410 to 1449 are reserved */
+#define MDIO_PMAPMD_PMDTRAINPATTERN(x)     /* PMD training pattern */  \
+                                       (1450 + (x)) /* lane0 to 3 */
+       /* Values 1454 to 1499 are reserved */
+#define MDIO_PMAPMD_TSTPAT             1500 /* Test-pattern ability */
+#define MDIO_PMAPMD_PRBSPATTSTCTRL     1501 /* PRBS pattern testing control */
+       /* Values 1502 to 1509 are reserved */
+#define MDIO_PMAPMD_SQWVTSTCTRL                1510 /* Square wave testing control */
+       /* Values 1511 to 1599 are reserved */
+#define MDIO_PMAPMD_PRBSTXERRCNT(x)         /* PRBS Tx Error Counter */ \
+                                       (1600 + (x)) /* lane0 to 9 */
+       /* Values 1610 to 1699 are reserved */
+#define MDIO_PMAPMD_PRBSRXERRCNT(x)         /* PRBS Rx Error Counter */ \
+                                       (1700 + (x)) /* lane0 to 9 */
+       /* Values 1710 to 1799 are reserved */
+#define MDIO_PMAPMD_TSYNCCAP           1800 /* TimeSync PMA/PMD capability */
+#define MDIO_PMAPMD_TSYNCTXMAXDLYL     1801 /* TimeSync PMAPMD TX MAXdelay L*/
+#define MDIO_PMAPMD_TSYNCTXMAXDLYH     1802 /* TimeSync PMAPMD TX MAXdelay H*/
+#define MDIO_PMAPMD_TSYNCTXMINDLYL     1803 /* TimeSync PMAPMD TX MINdelay L*/
+#define MDIO_PMAPMD_TSYNCTXMINDLYH     1804 /* TimeSync PMAPMD TX MINdelay H*/
+#define MDIO_PMAPMD_TSYNCRXMAXDLYL     1805 /* TimeSync PMAPMD RX MAXdelay L*/
+#define MDIO_PMAPMD_TSYNCRXMAXDLYH     1806 /* TimeSync PMAPMD RX MAXdelay H*/
+#define MDIO_PMAPMD_TSYNCRXMINDLYL     1807 /* TimeSync PMAPMD RX MINdelay L*/
+#define MDIO_PMAPMD_TSYNCRXMINDLYH     1808 /* TimeSync PMAPMD RX MINdelay H*/
+       /* Values 1809 to 32767 are reserved */
        /* Values 32768 to 65535 are vendor specific */
 
 /*
- * MDIO WIS registers.
- * Table 45-65
+ * WIS registers.
+ * Table 45-99
  */
 #define        MDIO_WIS_CTRL1          0       /* WIS control 1 */
 #define        MDIO_WIS_STAT1          1       /* WIS status 1 */
@@ -207,24 +317,13 @@
        /* Values 16 to 32 are reserved */
 #define        MDIO_WIS_10GSTAT3       33      /* 10G WIS status 3 */
        /* Values 34 to 36 are reserved */
-#define        MDIO_WIS_FARENDPBERRCNT 37      /* WIS far end path block error count*/
+#define        MDIO_WIS_10GFARENDPBERRCNT 37   /* 10G WIS far end path block errcnt */
        /* Value 38 is reserved */
-#define        MDIO_WIS_J1XMIT1        39      /* 10G WIS J1 transmit 1 */
-#define        MDIO_WIS_J1XMIT2        40      /* 10G WIS J1 transmit 2 */
-#define        MDIO_WIS_J1XMIT3        41      /* 10G WIS J1 transmit 3 */
-#define        MDIO_WIS_J1XMIT4        42      /* 10G WIS J1 transmit 4 */
-#define        MDIO_WIS_J1XMIT5        43      /* 10G WIS J1 transmit 5 */
-#define        MDIO_WIS_J1XMIT6        44      /* 10G WIS J1 transmit 6 */
-#define        MDIO_WIS_J1XMIT7        45      /* 10G WIS J1 transmit 7 */
-#define        MDIO_WIS_J1XMIT8        46      /* 10G WIS J1 transmit 8 */
-#define        MDIO_WIS_J1RECV1        47      /* 10G WIS J1 receive 1 */
-#define        MDIO_WIS_J1RECV2        48      /* 10G WIS J1 receive 2 */
-#define        MDIO_WIS_J1RECV3        49      /* 10G WIS J1 receive 3 */
-#define        MDIO_WIS_J1RECV4        50      /* 10G WIS J1 receive 4 */
-#define        MDIO_WIS_J1RECV5        51      /* 10G WIS J1 receive 5 */
-#define        MDIO_WIS_J1RECV6        52      /* 10G WIS J1 receive 6 */
-#define        MDIO_WIS_J1RECV7        53      /* 10G WIS J1 receive 7 */
-#define        MDIO_WIS_J1RECV8        54      /* 10G WIS J1 receive 8 */
+#define        MDIO_WIS_J1XMIT(x)              /* 10G WIS J1 transmit */            \
+                               (39 + ((x) / 2))/* 0to15. L8=even, H8=odd */
+
+#define        MDIO_WIS_J1RCV(x)               /* 10G WIS J1 receive */             \
+                               (47 + ((x) / 2))/* 0to15. L8=even, H8=odd */
 #define        MDIO_WIS_FARENDLBIPERR1 55      /* 10G WIS far end line BIP errors 1 */
 #define        MDIO_WIS_FARENDLBIPERR2 56      /* 10G WIS far end line BIP errors 2 */
 #define        MDIO_WIS_LBIPERR1       57      /* 10G WIS line BIP errors 1 */
@@ -232,28 +331,27 @@
 #define        MDIO_WIS_PBERRCNT       59      /* 10G WIS path block error count */
 #define        MDIO_WIS_SECBIPERRCNT   60      /* 10G WIS section BIP error count */
        /* Values 61 to 63 are reserved */
-#define        MDIO_WIS_J0XMIT1        64      /* 10G WIS J0 transmit 1 */
-#define        MDIO_WIS_J0XMIT2        65      /* 10G WIS J0 transmit 2 */
-#define        MDIO_WIS_J0XMIT3        66      /* 10G WIS J0 transmit 3 */
-#define        MDIO_WIS_J0XMIT4        67      /* 10G WIS J0 transmit 4 */
-#define        MDIO_WIS_J0XMIT5        68      /* 10G WIS J0 transmit 5 */
-#define        MDIO_WIS_J0XMIT6        69      /* 10G WIS J0 transmit 6 */
-#define        MDIO_WIS_J0XMIT7        70      /* 10G WIS J0 transmit 7 */
-#define        MDIO_WIS_J0XMIT8        71      /* 10G WIS J0 transmit 8 */
-#define        MDIO_WIS_J0RECV1        72      /* 10G WIS J0 receive 1 */
-#define        MDIO_WIS_J0RECV2        73      /* 10G WIS J0 receive 2 */
-#define        MDIO_WIS_J0RECV3        74      /* 10G WIS J0 receive 3 */
-#define        MDIO_WIS_J0RECV4        75      /* 10G WIS J0 receive 4 */
-#define        MDIO_WIS_J0RECV5        76      /* 10G WIS J0 receive 5 */
-#define        MDIO_WIS_J0RECV6        77      /* 10G WIS J0 receive 6 */
-#define        MDIO_WIS_J0RECV7        78      /* 10G WIS J0 receive 7 */
-#define        MDIO_WIS_J0RECV8        79      /* 10G WIS J0 receive 8 */
-       /* Values 80 to 32767 are reserved */
+#define        MDIO_WIS_J0XMIT(x)              /* 10G WIS J0 transmit */            \
+                               (64 + ((x) / 2))/* 0to15. L8=even, H8=odd */
+
+#define        MDIO_WIS_J0RCV(x)               /* 10G WIS J0 receive */             \
+                               (72 + ((x) / 2))/* 0to15. L8=even, H8=odd */
+       /* Values 80 to 1799 are reserved */
+#define MDIO_WIS_TSYNCCAP      1800 /* TimeSync WIS capability */
+#define MDIO_WIS_TSYNCTXMAXDLYL        1801 /* TimeSync WIS TX MAXdelay L*/
+#define MDIO_WIS_TSYNCTXMAXDLYH        1802 /* TimeSync WIS TX MAXdelay H*/
+#define MDIO_WIS_TSYNCTXMINDLYL        1803 /* TimeSync WIS TX MINdelay L*/
+#define MDIO_WIS_TSYNCTXMINDLYH        1804 /* TimeSync WIS TX MINdelay H*/
+#define MDIO_WIS_TSYNCRXMAXDLYL        1805 /* TimeSync WIS RX MAXdelay L*/
+#define MDIO_WIS_TSYNCRXMAXDLYH        1806 /* TimeSync WIS RX MAXdelay H*/
+#define MDIO_WIS_TSYNCRXMINDLYL        1807 /* TimeSync WIS RX MINdelay L*/
+#define MDIO_WIS_TSYNCRXMINDLYH        1808 /* TimeSync WIS RX MINdelay H*/
+       /* Values 1809 to 32767 are reserved */
        /* Values 32768 to 65535 are vendor specific */
 
 /*
- * MDIO PCS registers.
- * Table 45-82
+ * PCS registers.
+ * Table 45-119
  */
 #define        MDIO_PCS_CTRL1          0       /* PCS control 1 */
 #define        MDIO_PCS_STAT1          1       /* PCS status 1 */



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