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[src/trunk]: src/sys/arch/arm/rockchip Add support for Rockchip RK3399 SoC.



details:   https://anonhg.NetBSD.org/src/rev/a8e773500071
branches:  trunk
changeset: 365348:a8e773500071
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Aug 12 16:48:04 2018 +0000

description:
Add support for Rockchip RK3399 SoC.

diffstat:

 sys/arch/arm/rockchip/files.rockchip    |   15 +-
 sys/arch/arm/rockchip/rk3328_cru.c      |   18 +-
 sys/arch/arm/rockchip/rk3328_iomux.c    |  314 +++++++++++++++
 sys/arch/arm/rockchip/rk3399_cru.c      |  636 ++++++++++++++++++++++++++++++++
 sys/arch/arm/rockchip/rk3399_cru.h      |  353 +++++++++++++++++
 sys/arch/arm/rockchip/rk3399_iomux.c    |  464 +++++++++++++++++++++++
 sys/arch/arm/rockchip/rk3399_platform.h |   40 ++
 sys/arch/arm/rockchip/rk3399_pmucru.c   |  333 ++++++++++++++++
 sys/arch/arm/rockchip/rk3399_pmucru.h   |   72 +++
 sys/arch/arm/rockchip/rk_cru.c          |   14 +-
 sys/arch/arm/rockchip/rk_cru.h          |   21 +-
 sys/arch/arm/rockchip/rk_cru_pll.c      |    6 +-
 sys/arch/arm/rockchip/rk_gmac.c         |  214 +++++++--
 sys/arch/arm/rockchip/rk_iomux.c        |  317 ---------------
 sys/arch/arm/rockchip/rk_platform.c     |   62 +++-
 sys/arch/arm/rockchip/rk_usb.c          |  152 ++++++-
 16 files changed, 2610 insertions(+), 421 deletions(-)

diffs (truncated from 3425 to 300 lines):

diff -r e454c995820d -r a8e773500071 sys/arch/arm/rockchip/files.rockchip
--- a/sys/arch/arm/rockchip/files.rockchip      Sun Aug 12 16:34:28 2018 +0000
+++ b/sys/arch/arm/rockchip/files.rockchip      Sun Aug 12 16:48:04 2018 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: files.rockchip,v 1.14 2018/07/01 18:16:58 jmcneill Exp $
+#      $NetBSD: files.rockchip,v 1.15 2018/08/12 16:48:04 jmcneill Exp $
 #
 # Configuration info for Rockchip family SoCs
 #
@@ -19,10 +19,18 @@
 attach rkcru at fdt with rk3328_cru
 file   arch/arm/rockchip/rk3328_cru.c          rk3328_cru & soc_rk3328
 
+# RK3399 clock and reset unit
+attach rkcru at fdt with rk3399_cru
+file   arch/arm/rockchip/rk3399_cru.c          rk3399_cru & soc_rk3399
+attach rkcru at fdt with rk3399_pmucru
+file   arch/arm/rockchip/rk3399_pmucru.c       rk3399_pmucru & soc_rk3399
+
 # IOMUX control
 device rkiomux { }
-attach rkiomux at fdt with rk_iomux
-file   arch/arm/rockchip/rk_iomux.c            rk_iomux
+attach rkiomux at fdt with rk3328_iomux
+file   arch/arm/rockchip/rk3328_iomux.c        rk3328_iomux & soc_rk3328
+attach rkiomux at fdt with rk3399_iomux
+file   arch/arm/rockchip/rk3399_iomux.c        rk3399_iomux & soc_rk3399
 
 # GPIO
 device rkgpio: gpiobus
@@ -48,3 +56,4 @@
 # SOC parameters
 defflag        opt_soc.h                       SOC_ROCKCHIP
 defflag        opt_soc.h                       SOC_RK3328: SOC_ROCKCHIP
+defflag        opt_soc.h                       SOC_RK3399: SOC_ROCKCHIP
diff -r e454c995820d -r a8e773500071 sys/arch/arm/rockchip/rk3328_cru.c
--- a/sys/arch/arm/rockchip/rk3328_cru.c        Sun Aug 12 16:34:28 2018 +0000
+++ b/sys/arch/arm/rockchip/rk3328_cru.c        Sun Aug 12 16:48:04 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3328_cru.c,v 1.3 2018/07/01 18:15:19 jmcneill Exp $ */
+/* $NetBSD: rk3328_cru.c,v 1.4 2018/08/12 16:48:04 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.3 2018/07/01 18:15:19 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.4 2018/08/12 16:48:04 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -44,6 +44,7 @@
 #define        MISC_CON        0x0084  
 #define        CLKSEL_CON(n)   (0x0100 + (n) * 4)
 #define        CLKGATE_CON(n)  (0x0200 + (n) * 4)
+#define        SOFTRST_CON(n)  (0x0300 + (n) * 4)
 
 #define        GRF_SOC_CON4    0x0410
 #define        GRF_MAC_CON1    0x0904
@@ -131,6 +132,7 @@
        RK_ARM_RATE(  96000000, 1),
 };
 
+static const char * pll_parents[] = { "xin24m" };
 static const char * armclk_parents[] = { "apll", "gpll", "dpll", "npll" };
 static const char * aclk_bus_pre_parents[] = { "cpll", "gpll", "hdmiphy" };
 static const char * hclk_bus_pre_parents[] = { "aclk_bus_pre" };
@@ -151,31 +153,31 @@
 static const char * pclk_gmac_parents[] = { "aclk_gmac" };
 
 static struct rk_cru_clk rk3328_cru_clks[] = {
-       RK_PLL(RK3328_PLL_APLL, "apll", "xin24m",
+       RK_PLL(RK3328_PLL_APLL, "apll", pll_parents,
               PLL_CON(0),              /* con_base */
               0x80,                    /* mode_reg */
               __BIT(0),                /* mode_mask */
               __BIT(4),                /* lock_mask */
               pll_frac_rates),
-       RK_PLL(RK3328_PLL_DPLL, "dpll", "xin24m",
+       RK_PLL(RK3328_PLL_DPLL, "dpll", pll_parents,
               PLL_CON(8),              /* con_base */
               0x80,                    /* mode_reg */
               __BIT(4),                /* mode_mask */
               __BIT(3),                /* lock_mask */
               pll_norates),
-       RK_PLL(RK3328_PLL_CPLL, "cpll", "xin24m",
+       RK_PLL(RK3328_PLL_CPLL, "cpll", pll_parents,
               PLL_CON(16),             /* con_base */
               0x80,                    /* mode_reg */
               __BIT(8),                /* mode_mask */
               __BIT(2),                /* lock_mask */
               pll_rates),
-       RK_PLL(RK3328_PLL_GPLL, "gpll", "xin24m",
+       RK_PLL(RK3328_PLL_GPLL, "gpll", pll_parents,
               PLL_CON(24),             /* con_base */
               0x80,                    /* mode_reg */
               __BIT(12),               /* mode_mask */
               __BIT(1),                /* lock_mask */
               pll_frac_rates),
-       RK_PLL(RK3328_PLL_NPLL, "npll", "xin24m",
+       RK_PLL(RK3328_PLL_NPLL, "npll", pll_parents,
               PLL_CON(40),             /* con_base */
               0x80,                    /* mode_reg */
               __BIT(1),                /* mode_mask */
@@ -398,6 +400,8 @@
        sc->sc_clks = rk3328_cru_clks;
        sc->sc_nclks = __arraycount(rk3328_cru_clks);
 
+       sc->sc_softrst_base = SOFTRST_CON(0);
+
        if (rk_cru_attach(sc) != 0)
                return;
 
diff -r e454c995820d -r a8e773500071 sys/arch/arm/rockchip/rk3328_iomux.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/rockchip/rk3328_iomux.c      Sun Aug 12 16:48:04 2018 +0000
@@ -0,0 +1,314 @@
+/* $NetBSD: rk3328_iomux.c,v 1.1 2018/08/12 16:48:04 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rk3328_iomux.c,v 1.1 2018/08/12 16:48:04 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/mutex.h>
+#include <sys/kmem.h>
+#include <sys/lwp.h>
+
+#include <dev/fdt/fdtvar.h>
+#include <dev/fdt/syscon.h>
+
+#define        GRF_GPIO_P_REG(_bank, _idx)     (0x0100 + (_bank) * 0x10 + ((_idx) >> 3) * 4)
+#define         GRF_GPIO_P_CTL(_idx)           (0x3 << (((_idx) & 7) * 2))
+#define          GRF_GPIO_P_CTL_Z              0
+#define          GRF_GPIO_P_CTL_PULLUP         1
+#define          GRF_GPIO_P_CTL_PULLDOWN       2
+#define          GRF_GPIO_P_CTL_REPEATER       3
+#define          GRF_GPIO_P_CTL_MASK           0x3
+#define         GRF_GPIO_P_WRITE_EN(_idx)      (0x3 << (((_idx) & 7) * 2 + 16))
+
+#define        GRF_GPIO_E_REG(_bank, _idx)     (0x0200 + (_bank) * 0x10 + ((_idx) >> 3) * 4)
+#define         GRF_GPIO_E_CTL(_idx)           (0x3 << (((_idx) & 7) * 2))
+#define          GRF_GPIO_E_CTL_2MA            0
+#define          GRF_GPIO_E_CTL_4MA            1
+#define          GRF_GPIO_E_CTL_8MA            2
+#define          GRF_GPIO_E_CTL_12MA           3
+#define          GRF_GPIO_E_CTL_MASK           0x3
+#define         GRF_GPIO_E_WRITE_EN(_idx)      (0x3 << (((_idx) & 7) * 2 + 16))
+
+struct rk3328_iomux {
+       bus_size_t              base;
+       u_int                   type;
+#define        RK3328_IOMUX_TYPE_3BIT  0x01
+};
+
+struct rk3328_iomux_bank {
+       struct rk3328_iomux             iomux[4];
+};
+
+static const struct rk3328_iomux_bank rk3328_iomux_banks[] = {
+       [0] = {
+               .iomux = {
+                       [0] = { .base = 0x0000 },
+                       [1] = { .base = 0x0004 },
+                       [2] = { .base = 0x0008 },
+                       [3] = { .base = 0x000c },
+               },
+       },
+       [1] = {
+               .iomux = {
+                       [0] = { .base = 0x0010 },
+                       [1] = { .base = 0x0014 },
+                       [2] = { .base = 0x0018 },
+                       [3] = { .base = 0x001c },
+               }
+       },
+       [2] = {
+               .iomux = {
+                       [0] = { .base = 0x0020 },
+                       [1] = { .base = 0x0024, .type = RK3328_IOMUX_TYPE_3BIT },
+                       [2] = { .base = 0x002c, .type = RK3328_IOMUX_TYPE_3BIT },
+                       [3] = { .base = 0x0034 },
+               },
+       },
+       [3] = {
+               .iomux = {
+                       [0] = { .base = 0x0038, .type = RK3328_IOMUX_TYPE_3BIT },
+                       [1] = { .base = 0x0040, .type = RK3328_IOMUX_TYPE_3BIT },
+                       [2] = { .base = 0x0048 },
+                       [3] = { .base = 0x004c },
+               },
+       },
+};
+
+struct rk3328_iomux_conf {
+       const struct rk3328_iomux_bank *banks;
+       u_int nbanks;
+};
+
+static const struct rk3328_iomux_conf rk3328_iomux_conf = {
+       .banks = rk3328_iomux_banks,
+       .nbanks = __arraycount(rk3328_iomux_banks),
+};
+
+static const struct of_compat_data compat_data[] = {
+       { "rockchip,rk3328-pinctrl",    (uintptr_t)&rk3328_iomux_conf },
+       { NULL }
+};
+
+struct rk3328_iomux_softc {
+       device_t sc_dev;
+       struct syscon *sc_syscon;
+
+       const struct rk3328_iomux_conf *sc_conf;
+};
+
+#define        LOCK(sc)                \
+       syscon_lock((sc)->sc_syscon)
+#define        UNLOCK(sc)              \
+       syscon_unlock((sc)->sc_syscon)
+#define        RD4(sc, reg)            \
+       syscon_read_4((sc)->sc_syscon, (reg))
+#define        WR4(sc, reg, val)       \
+       syscon_write_4((sc)->sc_syscon, (reg), (val))
+
+static int     rk3328_iomux_match(device_t, cfdata_t, void *);
+static void    rk3328_iomux_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(rk3328_iomux, sizeof(struct rk3328_iomux_softc),
+       rk3328_iomux_match, rk3328_iomux_attach, NULL, NULL);
+
+static void
+rk3328_iomux_calc_iomux_reg(struct rk3328_iomux_softc *sc, u_int bank, u_int pin, bus_size_t *reg, uint32_t *mask)
+{
+       const struct rk3328_iomux_bank *banks = sc->sc_conf->banks;
+
+       KASSERT(bank < sc->sc_conf->nbanks);
+
+       *reg = banks[bank].iomux[pin / 8].base;
+       if (banks[bank].iomux[pin / 8].type & RK3328_IOMUX_TYPE_3BIT) {
+               if ((pin % 8) >= 5)
+                       *reg += 0x04;
+               const u_int bit = (pin % 8 % 5) * 3;
+               *mask = 7 << bit;
+       } else {
+               const u_int bit = (pin % 8) * 2;
+               *mask = 3 << bit;
+       }
+}
+
+static void
+rk3328_iomux_set_bias(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int bias)
+{
+       WR4(sc, GRF_GPIO_P_REG(bank, idx),
+           __SHIFTIN(GRF_GPIO_P_CTL_MASK, GRF_GPIO_P_WRITE_EN(idx)) |
+           __SHIFTIN(bias, GRF_GPIO_P_CTL(idx)));
+}
+
+static void
+rk3328_iomux_set_drive_strength(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int drv)
+{
+       WR4(sc, GRF_GPIO_E_REG(bank, idx),
+           __SHIFTIN(GRF_GPIO_E_CTL_MASK, GRF_GPIO_E_WRITE_EN(idx)) |
+           __SHIFTIN(drv, GRF_GPIO_E_CTL(idx)));
+}
+
+static void
+rk3328_iomux_set_mux(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int mux)
+{



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