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[src/trunk]: src/usr.sbin/tprof/arch Inline the values in amd_f10h_names[], w...



details:   https://anonhg.NetBSD.org/src/rev/068d31a69206
branches:  trunk
changeset: 363145:068d31a69206
user:      maxv <maxv%NetBSD.org@localhost>
date:      Fri Jul 13 08:09:21 2018 +0000

description:
Inline the values in amd_f10h_names[], we're not going to use defines for
each CPU model found in the wild.

diffstat:

 usr.sbin/tprof/arch/tprof_x86.c |  141 +++++++++++++++++++--------------------
 1 files changed, 70 insertions(+), 71 deletions(-)

diffs (156 lines):

diff -r 30655c681dae -r 068d31a69206 usr.sbin/tprof/arch/tprof_x86.c
--- a/usr.sbin/tprof/arch/tprof_x86.c   Fri Jul 13 07:56:29 2018 +0000
+++ b/usr.sbin/tprof/arch/tprof_x86.c   Fri Jul 13 08:09:21 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: tprof_x86.c,v 1.1 2018/07/13 07:56:29 maxv Exp $       */
+/*     $NetBSD: tprof_x86.c,v 1.2 2018/07/13 08:09:21 maxv Exp $       */
 
 /*
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -180,77 +180,76 @@
  * AMD Family 10h
  */
 static struct name_to_event amd_f10h_names[] = {
-       { "seg-load-all",               F10H_SEGMENT_REG_LOADS,         0x7f, true },
-       { "seg-load-es",                F10H_SEGMENT_REG_LOADS,         0x01, true },
-       { "seg-load-cs",                F10H_SEGMENT_REG_LOADS,         0x02, true },
-       { "seg-load-ss",                F10H_SEGMENT_REG_LOADS,         0x04, true },
-       { "seg-load-ds",                F10H_SEGMENT_REG_LOADS,         0x08, true },
-       { "seg-load-fs",                F10H_SEGMENT_REG_LOADS,         0x10, true },
-       { "seg-load-gs",                F10H_SEGMENT_REG_LOADS,         0x20, true },
-       { "seg-load-hs",                F10H_SEGMENT_REG_LOADS,         0x40, true },
-       { "l1cache-access",             F10H_DATA_CACHE_ACCESS,         0, true },
-       { "l1cache-miss",               F10H_DATA_CACHE_MISS,           0, true },
-       { "l1cache-refill",             F10H_DATA_CACHE_REFILL_FROM_L2, 0x1f, true },
-       { "l1cache-refill-invalid",     F10H_DATA_CACHE_REFILL_FROM_L2, 0x01, true },
-       { "l1cache-refill-shared",      F10H_DATA_CACHE_REFILL_FROM_L2, 0x02, true },
-       { "l1cache-refill-exclusive",   F10H_DATA_CACHE_REFILL_FROM_L2, 0x04, true },
-       { "l1cache-refill-owner",       F10H_DATA_CACHE_REFILL_FROM_L2, 0x08, true },
-       { "l1cache-refill-modified",    F10H_DATA_CACHE_REFILL_FROM_L2, 0x10, true },
-       { "l1cache-load",               F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x1f, true },
-       { "l1cache-load-invalid",       F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x01, true },
-       { "l1cache-load-shared",        F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x02, true },
-       { "l1cache-load-exclusive",     F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x04, true },
-       { "l1cache-load-owner",         F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x08, true },
-       { "l1cache-load-modified",      F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x10, true },
-       { "l1cache-writeback",          F10H_CACHE_LINES_EVICTED,       0x1f, true },
-       { "l1cache-writeback-invalid",  F10H_CACHE_LINES_EVICTED,       0x01, true },
-       { "l1cache-writeback-shared",   F10H_CACHE_LINES_EVICTED,       0x02, true },
-       { "l1cache-writeback-exclusive",F10H_CACHE_LINES_EVICTED,       0x04, true },
-       { "l1cache-writeback-owner",    F10H_CACHE_LINES_EVICTED,       0x08, true },
-       { "l1cache-writeback-modified", F10H_CACHE_LINES_EVICTED,       0x10, true },
-       { "l1DTLB-hit-all",             F10H_L1_DTLB_HIT,               0x07, true },
-       { "l1DTLB-hit-4Kpage",          F10H_L1_DTLB_HIT,               0x01, true },
-       { "l1DTLB-hit-2Mpage",          F10H_L1_DTLB_HIT,               0x02, true },
-       { "l1DTLB-hit-1Gpage",          F10H_L1_DTLB_HIT,               0x04, true },
-       { "l1DTLB-miss-all",            F10H_L1_DTLB_MISS,              0x07, true },
-       { "l1DTLB-miss-4Kpage",         F10H_L1_DTLB_MISS,              0x01, true },
-       { "l1DTLB-miss-2Mpage",         F10H_L1_DTLB_MISS,              0x02, true },
-       { "l1DTLB-miss-1Gpage",         F10H_L1_DTLB_MISS,              0x04, true },
-       { "l2DTLB-miss-all",            F10H_L2_DTLB_MISS,              0x03, true },
-       { "l2DTLB-miss-4Kpage",         F10H_L2_DTLB_MISS,              0x01, true },
-       { "l2DTLB-miss-2Mpage",         F10H_L2_DTLB_MISS,              0x02, true },
+       { "seg-load-all",               0x20, 0x7f, true },
+       { "seg-load-es",                0x20, 0x01, true },
+       { "seg-load-cs",                0x20, 0x02, true },
+       { "seg-load-ss",                0x20, 0x04, true },
+       { "seg-load-ds",                0x20, 0x08, true },
+       { "seg-load-fs",                0x20, 0x10, true },
+       { "seg-load-gs",                0x20, 0x20, true },
+       { "seg-load-hs",                0x20, 0x40, true },
+       { "l1cache-access",             0x40, 0x00, true },
+       { "l1cache-miss",               0x41, 0x00, true },
+       { "l1cache-refill",             0x42, 0x1f, true },
+       { "l1cache-refill-invalid",     0x42, 0x01, true },
+       { "l1cache-refill-shared",      0x42, 0x02, true },
+       { "l1cache-refill-exclusive",   0x42, 0x04, true },
+       { "l1cache-refill-owner",       0x42, 0x08, true },
+       { "l1cache-refill-modified",    0x42, 0x10, true },
+       { "l1cache-load",               0x43, 0x1f, true },
+       { "l1cache-load-invalid",       0x43, 0x01, true },
+       { "l1cache-load-shared",        0x43, 0x02, true },
+       { "l1cache-load-exclusive",     0x43, 0x04, true },
+       { "l1cache-load-owner",         0x43, 0x08, true },
+       { "l1cache-load-modified",      0x43, 0x10, true },
+       { "l1cache-writeback",          0x44, 0x1f, true },
+       { "l1cache-writeback-invalid",  0x44, 0x01, true },
+       { "l1cache-writeback-shared",   0x44, 0x02, true },
+       { "l1cache-writeback-exclusive",0x44, 0x04, true },
+       { "l1cache-writeback-owner",    0x44, 0x08, true },
+       { "l1cache-writeback-modified", 0x44, 0x10, true },
+       { "l1DTLB-hit-all",             0x4D, 0x07, true },
+       { "l1DTLB-hit-4Kpage",          0x4D, 0x01, true },
+       { "l1DTLB-hit-2Mpage",          0x4D, 0x02, true },
+       { "l1DTLB-hit-1Gpage",          0x4D, 0x04, true },
+       { "l1DTLB-miss-all",            0x45, 0x07, true },
+       { "l1DTLB-miss-4Kpage",         0x45, 0x01, true },
+       { "l1DTLB-miss-2Mpage",         0x45, 0x02, true },
+       { "l1DTLB-miss-1Gpage",         0x45, 0x04, true },
+       { "l2DTLB-miss-all",            0x46, 0x03, true },
+       { "l2DTLB-miss-4Kpage",         0x46, 0x01, true },
+       { "l2DTLB-miss-2Mpage",         0x46, 0x02, true },
        /* l2DTLB-miss-1Gpage: reserved on some revisions, so disabled */
-       { "l1ITLB-miss",                F10H_L1_ITLB_MISS,              0, true },
-       { "l2ITLB-miss-all",            F10H_L2_ITLB_MISS,              0x03, true },
-       { "l2ITLB-miss-4Kpage",         F10H_L2_ITLB_MISS,              0x01, true },
-       { "l2ITLB-miss-2Mpage",         F10H_L2_ITLB_MISS,              0x02, true },
-       { "mem-misalign-ref",           F10H_MISALIGNED_ACCESS,         0, true },
-       { "ins-fetch",                  F10H_INSTRUCTION_CACHE_FETCH,   0, true },
-       { "ins-fetch-miss",             F10H_INSTRUCTION_CACHE_MISS,    0, true },
-       { "ins-refill-l2",              F10H_INSTRUCTION_CACHE_REFILL_FROM_L2,  0, true },
-       { "ins-refill-sys",             F10H_INSTRUCTION_CACHE_REFILL_FROM_SYS, 0, true },
-       { "ins-fetch-stall",            F10H_INSTRUCTION_FETCH_STALL,   0, true },
-       { "ins-retired",                F10H_RETIRED_INSTRUCTIONS,      0, true },
-       { "ins-empty",                  F10H_DECODER_EMPTY,     0, true },
-       { "ops-retired",                F10H_RETIRED_UOPS,              0, true },
-       { "branch-retired",             F10H_RETIRED_BRANCH,            0, true },
-       { "branch-miss-retired",        F10H_RETIRED_MISPREDICTED_BRANCH,0, true },
-       { "branch-taken-retired",       F10H_RETIRED_TAKEN_BRANCH,      0, true },
-       { "branch-taken-miss-retired",  F10H_RETIRED_TAKEN_BRANCH_MISPREDICTED, 0, true },
-       { "branch-far-retired",         F10H_RETIRED_FAR_CONTROL_TRANSFER, 0, true },
-       { "branch-resync-retired",      F10H_RETIRED_BRANCH_RESYNC,     0, true },
-       { "branch-near-retired",        F10H_RETIRED_NEAR_RETURNS,      0, true },
-       { "branch-near-miss-retired",   F10H_RETIRED_NEAR_RETURNS_MISPREDICTED, 0, true },
-       { "branch-indirect-miss-retired", F10H_RETIRED_INDIRECT_BRANCH_MISPREDICTED,    0, true },
-       { "int-hw",                     F10H_INTERRUPTS_TAKEN,          0, true },
-       { "int-cycles-masked",          F10H_INTERRUPTS_MASKED_CYCLES,  0, true },
-       { "int-cycles-masked-pending",
-           F10H_INTERRUPTS_MASKED_CYCLES_INTERRUPT_PENDING, 0, true },
-       { "fpu-exceptions",             F10H_FPU_EXCEPTIONS, 0, true },
-       { "break-match0",               F10H_DR0_BREAKPOINT_MATCHES,    0, true },
-       { "break-match1",               F10H_DR1_BREAKPOINT_MATCHES,    0, true },
-       { "break-match2",               F10H_DR2_BREAKPOINT_MATCHES,    0, true },
-       { "break-match3",               F10H_DR3_BREAKPOINT_MATCHES,    0, true },
+       { "l1ITLB-miss",                0x84, 0x00, true },
+       { "l2ITLB-miss-all",            0x85, 0x03, true },
+       { "l2ITLB-miss-4Kpage",         0x85, 0x01, true },
+       { "l2ITLB-miss-2Mpage",         0x85, 0x02, true },
+       { "mem-misalign-ref",           0x47, 0x00, true },
+       { "ins-fetch",                  0x80, 0x00, true },
+       { "ins-fetch-miss",             0x81, 0x00, true },
+       { "ins-refill-l2",              0x82, 0x00, true },
+       { "ins-refill-sys",             0x83, 0x00, true },
+       { "ins-fetch-stall",            0x87, 0x00, true },
+       { "ins-retired",                0xC0, 0x00, true },
+       { "ins-empty",                  0xD0, 0x00, true },
+       { "ops-retired",                0xC1, 0x00, true },
+       { "branch-retired",             0xC2, 0x00, true },
+       { "branch-miss-retired",        0xC3, 0x00, true },
+       { "branch-taken-retired",       0xC4, 0x00, true },
+       { "branch-taken-miss-retired",  0xC5, 0x00, true },
+       { "branch-far-retired",         0xC6, 0x00, true },
+       { "branch-resync-retired",      0xC7, 0x00, true },
+       { "branch-near-retired",        0xC8, 0x00, true },
+       { "branch-near-miss-retired",   0xC9, 0x00, true },
+       { "branch-indirect-miss-retired", 0xCA, 0x00, true },
+       { "int-hw",                     0xCF, 0x00, true },
+       { "int-cycles-masked",          0xCD, 0x00, true },
+       { "int-cycles-masked-pending",  0xCE, 0x00, true },
+       { "fpu-exceptions",             0xDB, 0x00, true },
+       { "break-match0",               0xDC, 0x00, true },
+       { "break-match1",               0xDD, 0x00, true },
+       { "break-match2",               0xDE, 0x00, true },
+       { "break-match3",               0xDF, 0x00, true },
 };
 
 static struct event_table amd_f10h = {



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