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[src/trunk]: src/sys/dev/pci No binary change:



details:   https://anonhg.NetBSD.org/src/rev/d09cffe3ae3c
branches:  trunk
changeset: 361078:d09cffe3ae3c
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Thu Apr 12 02:15:07 2018 +0000

description:
No binary change:
- Sort registers.
- Lowercase hexadecimal value.

diffstat:

 sys/dev/pci/if_wmreg.h |  66 +++++++++++++++++++++++++-------------------------
 1 files changed, 33 insertions(+), 33 deletions(-)

diffs (223 lines):

diff -r 425e48c56152 -r d09cffe3ae3c sys/dev/pci/if_wmreg.h
--- a/sys/dev/pci/if_wmreg.h    Wed Apr 11 23:20:15 2018 +0000
+++ b/sys/dev/pci/if_wmreg.h    Thu Apr 12 02:15:07 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wmreg.h,v 1.106 2018/04/10 08:18:38 msaitoh Exp $   */
+/*     $NetBSD: if_wmreg.h,v 1.107 2018/04/12 02:15:07 msaitoh Exp $   */
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -511,15 +511,15 @@
 #define EECD_SEC1VAL   (1U << 22)      /* Sector One Valid */
 #define EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */
 
+#define        WMREG_FEXTNVM6  0x0010  /* Future Extended NVM 6 */
+#define        FEXTNVM6_K1_OFF_ENABLE  __BIT(31)
+
 #define        WMREG_EERD      0x0014  /* EEPROM read */
 #define        EERD_DONE       0x02    /* done bit */
 #define        EERD_START      0x01    /* First bit for telling part to start operation */
 #define        EERD_ADDR_SHIFT 2       /* Shift to the address bits */
 #define        EERD_DATA_SHIFT 16      /* Offset to data in EEPROM read/write registers */
 
-#define        WMREG_FEXTNVM6  0x0010  /* Future Extended NVM 6 */
-#define        FEXTNVM6_K1_OFF_ENABLE  __BIT(31)
-
 #define        WMREG_CTRL_EXT  0x0018  /* Extended Device Control Register */
 #define        CTRL_EXT_NSICR          __BIT(0) /* Non Interrupt clear on read */
 #define        CTRL_EXT_GPI_EN(x)      (1U << (x)) /* gpin interrupt enable */
@@ -544,14 +544,14 @@
 #define        CTRL_EXT_SDLPE          (1U << 18) /* SerDes Low Power Enable */
 #define        CTRL_EXT_DMA_DYN_CLK    (1U << 19) /* DMA Dynamic Gating Enable */
 #define        CTRL_EXT_PHYPDEN        __BIT(20)
-#define        CTRL_EXT_LINK_MODE_MASK         0x00C00000
+#define        CTRL_EXT_LINK_MODE_MASK         0x00c00000
 #define        CTRL_EXT_LINK_MODE_GMII         0x00000000
 #define        CTRL_EXT_LINK_MODE_KMRN         0x00000000
 #define        CTRL_EXT_LINK_MODE_1000KX       0x00400000
 #define        CTRL_EXT_LINK_MODE_SGMII        0x00800000
 #define        CTRL_EXT_LINK_MODE_PCIX_SERDES  0x00800000
-#define        CTRL_EXT_LINK_MODE_TBI          0x00C00000
-#define        CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
+#define        CTRL_EXT_LINK_MODE_TBI          0x00c00000
+#define        CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00c00000
 #define        CTRL_EXT_EIAME          __BIT(24) /* Extended Interrupt Auto Mask En */
 #define CTRL_EXT_I2C_ENA       0x02000000  /* I2C enable */
 #define        CTRL_EXT_DRV_LOAD       0x10000000
@@ -599,8 +599,8 @@
 #define        WMREG_FCT       0x0030  /* Flow Control Type */
 
 #define        WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */
-#define        KUMCTRLSTA_MASK                 0x0000FFFF
-#define        KUMCTRLSTA_OFFSET               0x001F0000
+#define        KUMCTRLSTA_MASK                 0x0000ffff
+#define        KUMCTRLSTA_OFFSET               0x001f0000
 #define        KUMCTRLSTA_OFFSET_SHIFT         16
 #define        KUMCTRLSTA_REN                  0x00200000
 
@@ -612,8 +612,8 @@
 #define        KUMCTRLSTA_OFFSET_K1_CONFIG     0x00000007
 #define        KUMCTRLSTA_OFFSET_INB_PARAM     0x00000009
 #define        KUMCTRLSTA_OFFSET_HD_CTRL       0x00000010
-#define        KUMCTRLSTA_OFFSET_M2P_SERDES    0x0000001E
-#define        KUMCTRLSTA_OFFSET_M2P_MODES     0x0000001F
+#define        KUMCTRLSTA_OFFSET_M2P_SERDES    0x0000001e
+#define        KUMCTRLSTA_OFFSET_M2P_MODES     0x0000001f
 
 /* FIFO Control */
 #define        KUMCTRLSTA_FIFO_CTRL_RX_BYPASS  0x0008
@@ -638,7 +638,7 @@
 #define        KUMCTRLSTA_OPMODE_INBAND_MDIO 0x0004
 
 #define        WMREG_VET       0x0038  /* VLAN Ethertype */
-#define        WMREG_MDPHYA    0x003C  /* PHY address - RW */
+#define        WMREG_MDPHYA    0x003c  /* PHY address - RW */
 
 #define WMREG_FEXTNVM3 0x003c  /* Future Extended NVM 3 */
 #define FEXTNVM3_PHY_CFG_COUNTER_MASK  __BITS(27, 26)
@@ -795,7 +795,7 @@
 #define        WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */
 #define        WMREG_RDBAL(x) \
        ((x) < 4 ? (0x02800 + ((x) * 0x100)) :  \
-           (0x0C000 + ((x) * 0x40)))
+           (0x0c000 + ((x) * 0x40)))
 
 #define        WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */
 #define        WMREG_RDBAH(x) \
@@ -826,12 +826,12 @@
 #define        WMREG_OLD_RDH0  0x0120  /* Receive Descriptor Head (ring 0) */
 #define        WMREG_RDH(x) \
        ((x) < 4 ? (0x02810 + ((x) * 0x100)) :  \
-           (0x0C010 + ((x) * 0x40)))
+           (0x0c010 + ((x) * 0x40)))
 
 #define        WMREG_OLD_RDT0  0x0128  /* Receive Descriptor Tail (ring 0) */
 #define        WMREG_RDT(x) \
        ((x) < 4 ? (0x02818 + ((x) * 0x100)) :  \
-           (0x0C018 + ((x) * 0x40)))
+           (0x0c018 + ((x) * 0x40)))
 
 #define        WMREG_RXDCTL(x) \
        ((x) < 4 ? (0x02828 + ((x) * 0x100)) :  \
@@ -851,11 +851,11 @@
 #define        WMREG_OLD_RDH1  0x0148
 #define        WMREG_OLD_RDT1  0x0150
 #define        WMREG_OLD_FCRTH 0x0160  /* Flow Control Rx Threshold Hi (OLD) */
-#define        WMREG_FCRTL     0x2160  /* Flow Control Rx Threshold Lo */
+#define        WMREG_FCRTH     0x2168  /* Flow Control Rx Threhsold Hi */
 #define        FCRTH_DFLT      0x00008000
 
 #define        WMREG_OLD_FCRTL 0x0168  /* Flow Control Rx Threshold Lo (OLD) */
-#define        WMREG_FCRTH     0x2168  /* Flow Control Rx Threhsold Hi */
+#define        WMREG_FCRTL     0x2160  /* Flow Control Rx Threshold Lo */
 #define        FCRTL_DFLT      0x00004000
 #define        FCRTL_XONE      0x80000000      /* Enable XON frame transmission */
 
@@ -898,8 +898,8 @@
 #define        TX_COLLISION_DISTANCE_FDX       64
 
 #define        WMREG_TCTL_EXT  0x0404  /* Transmit Control Register */
-#define        TCTL_EXT_BST_MASK       0x000003FF /* Backoff Slot Time */
-#define        TCTL_EXT_GCEX_MASK      0x000FFC00 /* Gigabit Carry Extend Padding */
+#define        TCTL_EXT_BST_MASK       0x000003ff /* Backoff Slot Time */
+#define        TCTL_EXT_GCEX_MASK      0x000ffc00 /* Gigabit Carry Extend Padding */
 
 #define        DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
 
@@ -920,27 +920,27 @@
 #define        WMREG_OLD_TDBAL 0x0420  /* Transmit Descriptor Base Lo */
 #define        WMREG_TDBAL(x) \
        ((x) < 4 ? (0x03800 + ((x) * 0x100)) :  \
-           (0x0E000 + ((x) * 0x40)))
+           (0x0e000 + ((x) * 0x40)))
 
 #define        WMREG_OLD_TDBAH 0x0424  /* Transmit Descriptor Base Hi */
 #define        WMREG_TDBAH(x)\
        ((x) < 4 ? (0x03804 + ((x) * 0x100)) :  \
-           (0x0E004 + ((x) * 0x40)))
+           (0x0e004 + ((x) * 0x40)))
 
 #define        WMREG_OLD_TDLEN 0x0428  /* Transmit Descriptor Length */
 #define        WMREG_TDLEN(x) \
        ((x) < 4 ? (0x03808 + ((x) * 0x100)) :  \
-           (0x0E008 + ((x) * 0x40)))
+           (0x0e008 + ((x) * 0x40)))
 
 #define        WMREG_OLD_TDH   0x0430  /* Transmit Descriptor Head */
 #define        WMREG_TDH(x) \
        ((x) < 4 ? (0x03810 + ((x) * 0x100)) :  \
-           (0x0E010 + ((x) * 0x40)))
+           (0x0e010 + ((x) * 0x40)))
 
 #define        WMREG_OLD_TDT   0x0438  /* Transmit Descriptor Tail */
 #define WMREG_TDT(x) \
        ((x) < 4 ? (0x03818 + ((x) * 0x100)) :  \
-           (0x0E018 + ((x) * 0x40)))
+           (0x0e018 + ((x) * 0x40)))
 
 #define        WMREG_OLD_TIDV  0x0440  /* Transmit Delay Interrupt Value */
 #define        WMREG_TIDV      0x3820
@@ -986,7 +986,7 @@
 #define EXTCNFCTR_MDIO_SW_OWNERSHIP    0x00000020
 #define EXTCNFCTR_MDIO_HW_OWNERSHIP    0x00000040
 #define EXTCNFCTR_GATE_PHY_CFG         0x00000080
-#define EXTCNFCTR_EXT_CNF_POINTER      0x0FFF0000
+#define EXTCNFCTR_EXT_CNF_POINTER      0x0fff0000
 
 #define WMREG_EXTCNFSIZE 0x0f08  /* Extended Configuration Size */
 #define EXTCNFSIZE_LENGTH      __BITS(23, 16)
@@ -1066,7 +1066,7 @@
 #define WMREG_EICS     0x01520  /* Ext. Interrupt Cause Set - WO */
 #define WMREG_EIMS     0x01524  /* Ext. Interrupt Mask Set/Read - RW */
 #define WMREG_EIMC     0x01528  /* Ext. Interrupt Mask Clear - WO */
-#define WMREG_EIAC     0x0152C  /* Ext. Interrupt Auto Clear - RW */
+#define WMREG_EIAC     0x0152c  /* Ext. Interrupt Auto Clear - RW */
 #define WMREG_EIAM     0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
 
 #define WMREG_EICR     0x01580  /* Ext. Interrupt Cause Read - R/clr */
@@ -1083,11 +1083,11 @@
 #define EITR_COUNTER_MASK_82575        __BITS(31,16)
 #define EITR_CNT_INGR          __BIT(31) /* does not overwrite counter */
 
-#define WMREG_EITR_82574(x)    (0x000E8 + (0x4 * (x)))
+#define WMREG_EITR_82574(x)    (0x000e8 + (0x4 * (x)))
 #define EITR_ITR_INT_MASK_82574        __BITS(15, 0)
 
 #define        WMREG_RXPBS     0x2404  /* Rx Packet Buffer Size  */
-#define RXPBS_SIZE_MASK_82576  0x0000007F
+#define RXPBS_SIZE_MASK_82576  0x0000007f
 
 #define        WMREG_RDFH      0x2410  /* Receive Data FIFO Head */
 #define        WMREG_RDFT      0x2418  /* Receive Data FIFO Tail */
@@ -1494,7 +1494,7 @@
 #define INVM_MAJOR     __BITS(9,4)
 
 /* Word definitions for ID LED Settings */
-#define ID_LED_RESERVED_FFFF 0xFFFF
+#define ID_LED_RESERVED_FFFF 0xffff
 
 /* ich8 flash control */
 #define ICH_FLASH_COMMAND_TIMEOUT            5000    /* 5000 uSecs - adjusted */
@@ -1530,7 +1530,7 @@
 #define ICH_FLASH_FRACC    0x0050
 #define ICH_FLASH_FREG0    0x0054
 #define ICH_FLASH_FREG1    0x0058
-#define ICH_FLASH_FREG2    0x005C
+#define ICH_FLASH_FREG2    0x005c
 #define ICH_FLASH_FREG3    0x0060
 #define ICH_FLASH_FPR0     0x0074
 #define ICH_FLASH_FPR1     0x0078
@@ -1540,10 +1540,10 @@
 #define ICH_FLASH_OPTYPE   0x0096
 #define ICH_FLASH_OPMENU   0x0098
 
-#define ICH_FLASH_REG_MAPSIZE      0x00A0
+#define ICH_FLASH_REG_MAPSIZE      0x00a0
 #define ICH_FLASH_SECTOR_SIZE      4096
-#define ICH_GFPREG_BASE_MASK       0x1FFF
-#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
+#define ICH_GFPREG_BASE_MASK       0x1fff
+#define ICH_FLASH_LINEAR_ADDR_MASK 0x00ffffff
 
 #define ICH_NVM_SIG_WORD       0x13
 #define ICH_NVM_SIG_MASK       0xc000



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