Source-Changes-HG archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

[src/trunk]: src/sys/dev/mii switch to using OpenBSD eehpy(4) code to drive m...



details:   https://anonhg.NetBSD.org/src/rev/bb24a516161d
branches:  trunk
changeset: 362594:bb24a516161d
user:      jdolecek <jdolecek%NetBSD.org@localhost>
date:      Sat Jun 16 17:44:53 2018 +0000

description:
switch to using OpenBSD eehpy(4) code to drive maphy(4), synchronizing support
for several special PHY conditions, particularly:
- Properly re-initialise the PHY upon resume
- Store next page in the Link Partner Next Page register for compatibility
  with 802.3ab on 88E3016 PHYs.  Fixes some autonegotiation problems on msk(4)
- Make 88E3016 actually work
- Make sure page 0 is selected when we initialize the PHY.  Fixes problems
  with the eephy(4) that attaches to nfe(4) on machines like the Sun Ultra 40.
  (we had condition for this, now the page 0 is selected for any PHY type)
- Disable fiber/copper auto-selection on the 88E1111 if it is in RGMII mode, to
  work around the fact that the onboard PHYs attached to nfe(4) on the Sun
  X4100 M2 have fiber/copper auto-selection enabled even though the interfaces
  are clearly copper-only

make sure to also add appropriate licenses, since basically nothing
really significant remains out of previous code

use FreeBSD <dev/mii/e1000reg.h> for register definitions as a base instead
of OpenBSD <dev/mii/eephyreg.h>, since it has some extra definitions for some
3016 bits, but add the several extra bits from OpenBSD needed by the code;
removed no longed used <dev/mii/makphyreg.h>

tested with PHY 88E1111, there no particular change observed - the
link status works as it did before, just now it does media nego
even before the interface is up

should however fix 88E3016 support and hence PR kern/49270 and PR kern/53301

diffstat:

 sys/dev/mii/e1000phyreg.h |  384 ++++++++++++++++++++++++++++++++++++++++++++++
 sys/dev/mii/makphy.c      |  292 +++++++++++++++++++++++-----------
 sys/dev/mii/makphyreg.h   |  116 -------------
 3 files changed, 583 insertions(+), 209 deletions(-)

diffs (truncated from 922 to 300 lines):

diff -r 6dc0c490853b -r bb24a516161d sys/dev/mii/e1000phyreg.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/mii/e1000phyreg.h Sat Jun 16 17:44:53 2018 +0000
@@ -0,0 +1,384 @@
+/*     $NetBSD: e1000phyreg.h,v 1.1 2018/06/16 17:44:53 jdolecek Exp $ */
+/* $FreeBSD: head/sys/dev/mii/e1000phyreg.h 326022 2017-11-20 19:36:21Z pfg $ */
+/*-
+ * Principal Author: Parag Patel
+ * Copyright (c) 2001
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Additional Copyright (c) 2001 by Traakan Software under same licence.
+ * Secondary Author: Matthew Jacob
+ */
+
+/*-
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Derived by information released by Intel under the following license:
+ *
+ * Copyright (c) 1999 - 2001, Intel Corporation 
+ * 
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions are met:
+ * 
+ *  1. Redistributions of source code must retain the above copyright notice, 
+ *     this list of conditions and the following disclaimer.
+ * 
+ *  2. Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ * 
+ *  3. Neither the name of Intel Corporation nor the names of its contributors 
+ *     may be used to endorse or promote products derived from this software 
+ *     without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/*
+ * Marvell E1000 PHY registers
+ */
+
+#define E1000_MAX_REG_ADDRESS          0x1F
+
+#define E1000_CR                       0x00    /* control register */
+#define E1000_CR_SPEED_SELECT_MSB      0x0040
+#define E1000_CR_COLL_TEST_ENABLE      0x0080
+#define E1000_CR_FULL_DUPLEX           0x0100
+#define E1000_CR_RESTART_AUTO_NEG      0x0200
+#define E1000_CR_ISOLATE               0x0400
+#define E1000_CR_POWER_DOWN            0x0800
+#define E1000_CR_AUTO_NEG_ENABLE       0x1000
+#define E1000_CR_SPEED_SELECT_LSB      0x2000
+#define E1000_CR_LOOPBACK              0x4000
+#define E1000_CR_RESET                 0x8000
+
+#define E1000_CR_SPEED_1000            0x0040
+#define E1000_CR_SPEED_100             0x2000
+#define E1000_CR_SPEED_10              0x0000
+
+#define E1000_SR                       0x01    /* status register */
+#define E1000_SR_EXTENDED              0x0001
+#define E1000_SR_JABBER_DETECT         0x0002
+#define E1000_SR_LINK_STATUS           0x0004
+#define E1000_SR_AUTO_NEG              0x0008
+#define E1000_SR_REMOTE_FAULT          0x0010
+#define E1000_SR_AUTO_NEG_COMPLETE     0x0020
+#define E1000_SR_PREAMBLE_SUPPRESS     0x0040
+#define E1000_SR_EXTENDED_STATUS       0x0100
+#define E1000_SR_100T2                 0x0200
+#define E1000_SR_100T2_FD              0x0400
+#define E1000_SR_10T                   0x0800
+#define E1000_SR_10T_FD                        0x1000
+#define E1000_SR_100TX                 0x2000
+#define E1000_SR_100TX_FD              0x4000
+#define E1000_SR_100T4                 0x8000
+
+#define E1000_ID1                      0x02    /* ID register 1 */
+#define E1000_ID2                      0x03    /* ID register 2 */
+#define E1000_ID_88E1000               0x01410C50
+#define E1000_ID_88E1000S              0x01410C40
+#define E1000_ID_88E1011               0x01410C20
+#define E1000_ID_MASK                  0xFFFFFFF0
+
+#define E1000_AR                       0x04    /* autonegotiation advertise reg */
+#define E1000_AR_SELECTOR_FIELD                0x0001
+#define E1000_AR_10T                   0x0020
+#define E1000_AR_10T_FD                        0x0040
+#define E1000_AR_100TX                 0x0080
+#define E1000_AR_100TX_FD              0x0100
+#define E1000_AR_100T4                 0x0200
+#define E1000_AR_PAUSE                 0x0400
+#define E1000_AR_ASM_DIR               0x0800
+#define E1000_AR_REMOTE_FAULT          0x2000
+#define E1000_AR_NEXT_PAGE             0x8000
+#define E1000_AR_SPEED_MASK            0x01E0
+
+/* Autonegotiation register bits for fiber cards (Alaska Only!) */
+#define E1000_FA_1000X_FD              0x0020
+#define E1000_FA_1000X                 0x0040
+#define E1000_FA_SYM_PAUSE             0x0080
+#define E1000_FA_ASYM_PAUSE            0x0100
+#define E1000_FA_FAULT1                        0x1000
+#define E1000_FA_FAULT2                        0x2000
+#define E1000_FA_NEXT_PAGE             0x8000
+
+#define E1000_LPAR                     0x05    /* autoneg link partner abilities reg */
+#define E1000_LPAR_SELECTOR_FIELD      0x0001
+#define E1000_LPAR_10T                 0x0020
+#define E1000_LPAR_10T_FD              0x0040
+#define E1000_LPAR_100TX               0x0080
+#define E1000_LPAR_100TX_FD            0x0100
+#define E1000_LPAR_100T4               0x0200
+#define E1000_LPAR_PAUSE               0x0400
+#define E1000_LPAR_ASM_DIR             0x0800
+#define E1000_LPAR_REMOTE_FAULT                0x2000
+#define E1000_LPAR_ACKNOWLEDGE         0x4000
+#define E1000_LPAR_NEXT_PAGE           0x8000
+
+/* autoneg link partner ability register bits for fiber cards (Alaska Only!) */
+#define E1000_FPAR_1000X_FD            0x0020
+#define E1000_FPAR_1000X               0x0040
+#define E1000_FPAR_SYM_PAUSE           0x0080
+#define E1000_FPAR_ASYM_PAUSE          0x0100
+#define E1000_FPAR_FAULT1              0x1000
+#define E1000_FPAR_FAULT2              0x2000
+#define E1000_FPAR_ACK                 0x4000
+#define E1000_FPAR_NEXT_PAGE           0x8000
+
+#define E1000_ER                       0x06    /* autoneg expansion reg */
+#define E1000_ER_LP_NWAY               0x0001
+#define E1000_ER_PAGE_RXD              0x0002
+#define E1000_ER_NEXT_PAGE             0x0004
+#define E1000_ER_LP_NEXT_PAGE          0x0008
+#define E1000_ER_PAR_DETECT_FAULT      0x0100
+
+#define E1000_NPTX                     0x07    /* autoneg next page TX */
+#define E1000_NPTX_MSG_CODE_FIELD      0x0001
+#define E1000_NPTX_TOGGLE              0x0800
+#define E1000_NPTX_ACKNOWLDGE2         0x1000
+#define E1000_NPTX_MSG_PAGE            0x2000
+#define E1000_NPTX_NEXT_PAGE           0x8000
+
+#define E1000_RNPR                     0x08    /* autoneg link-partner (?) next page */
+#define E1000_RNPR_MSG_CODE_FIELD      0x0001
+#define E1000_RNPR_TOGGLE              0x0800
+#define E1000_RNPR_ACKNOWLDGE2         0x1000
+#define E1000_RNPR_MSG_PAGE            0x2000
+#define E1000_RNPR_ACKNOWLDGE          0x4000
+#define E1000_RNPR_NEXT_PAGE           0x8000
+
+#define E1000_1GCR                     0x09    /* 1000T (1G) control reg */
+#define E1000_1GCR_ASYM_PAUSE          0x0080
+#define E1000_1GCR_1000T               0x0100
+#define E1000_1GCR_1000T_FD            0x0200
+#define E1000_1GCR_REPEATER_DTE                0x0400
+#define E1000_1GCR_MS_VALUE            0x0800
+#define E1000_1GCR_MS_ENABLE           0x1000
+#define E1000_1GCR_TEST_MODE_NORMAL    0x0000
+#define E1000_1GCR_TEST_MODE_1         0x2000
+#define E1000_1GCR_TEST_MODE_2         0x4000
+#define E1000_1GCR_TEST_MODE_3         0x6000
+#define E1000_1GCR_TEST_MODE_4         0x8000
+#define E1000_1GCR_SPEED_MASK          0x0300
+
+#define E1000_1GSR                     0x0A    /* 1000T (1G) status reg */
+#define E1000_1GSR_IDLE_ERROR_CNT      0x0000
+#define E1000_1GSR_ASYM_PAUSE_DIR      0x0100
+#define E1000_1GSR_LP                  0x0400
+#define E1000_1GSR_LP_FD               0x0800
+#define E1000_1GSR_REMOTE_RX_STATUS    0x1000
+#define E1000_1GSR_LOCAL_RX_STATUS     0x2000
+#define E1000_1GSR_MS_CONFIG_RES       0x4000
+#define E1000_1GSR_MS_CONFIG_FAULT     0x8000
+
+#define E1000_ESR                      0x0F    /* IEEE extended status reg */
+#define E1000_ESR_1000T                        0x1000
+#define E1000_ESR_1000T_FD             0x2000
+#define E1000_ESR_1000X                        0x4000
+#define E1000_ESR_1000X_FD             0x8000
+
+#define E1000_TX_POLARITY_MASK         0x0100
+#define E1000_TX_NORMAL_POLARITY       0
+
+#define E1000_AUTO_POLARITY_DISABLE    0x0010
+
+#define E1000_SCR                      0x10    /* special control register */
+#define E1000_SCR_JABBER_DISABLE       0x0001
+#define E1000_SCR_POLARITY_REVERSAL    0x0002
+#define E1000_SCR_SQE_TEST             0x0004
+#define E1000_SCR_INT_FIFO_DISABLE     0x0008
+#define E1000_SCR_CLK125_DISABLE       0x0010
+#define E1000_SCR_MDI_MANUAL_MODE      0x0000
+#define E1000_SCR_MDIX_MANUAL_MODE     0x0020
+#define E1000_SCR_AUTO_X_1000T         0x0040
+#define E1000_SCR_AUTO_X_MODE          0x0060
+#define E1000_SCR_10BT_EXT_ENABLE      0x0080
+#define E1000_SCR_MII_5BIT_ENABLE      0x0100
+#define E1000_SCR_SCRAMBLER_DISABLE    0x0200
+#define E1000_SCR_FORCE_LINK_GOOD      0x0400
+#define E1000_SCR_ASSERT_CRS_ON_TX     0x0800
+#define E1000_SCR_RX_FIFO_DEPTH_6      0x0000
+#define E1000_SCR_RX_FIFO_DEPTH_8      0x1000
+#define E1000_SCR_RX_FIFO_DEPTH_10     0x2000
+#define E1000_SCR_RX_FIFO_DEPTH_12     0x3000
+#define E1000_SCR_TX_FIFO_DEPTH_6      0x0000
+#define E1000_SCR_TX_FIFO_DEPTH_8      0x4000
+#define E1000_SCR_TX_FIFO_DEPTH_10     0x8000
+#define E1000_SCR_TX_FIFO_DEPTH_12     0xC000
+
+/* 88E3016 only */
+#define        E1000_SCR_AUTO_MDIX             0x0030
+#define        E1000_SCR_SIGDET_POLARITY       0x0040
+#define        E1000_SCR_EXT_DISTANCE          0x0080
+#define        E1000_SCR_FEFI_DISABLE          0x0100
+#define        E1000_SCR_NLP_GEN_DISABLE       0x0800
+#define        E1000_SCR_LPNP                  0x1000
+#define        E1000_SCR_NLP_CHK_DISABLE       0x2000
+#define        E1000_SCR_EN_DETECT             0x4000
+
+#define E1000_SCR_EN_DETECT_MASK       0x0300
+
+#define E3000_SCR_SCRAMBLER_DISABLE    0x0200
+#define E3000_SCR_REG8_NEXT_PAGE       0x1000
+#define E3000_SCR_EN_DETECT_MASK       0x4000
+
+/* 88E1112 page 1 fiber specific control */
+#define E1000_SCR_FIB_TX_DIS           0x0008
+#define E1000_SCR_FIB_SIGDET_POLARITY  0x0200
+#define E1000_SCR_FIB_FORCE_LINK       0x0400
+
+/* 88E1112 page 2 */
+#define E1000_SCR_MODE_MASK            0x0380
+#define E1000_SCR_MODE_AUTO            0x0180
+#define E1000_SCR_MODE_COPPER          0x0280
+#define E1000_SCR_MODE_1000BX          0x0380
+
+/* 88E1116 page 0 */
+#define        E1000_SCR_POWER_DOWN            0x0004
+/* 88E1116, 88E1149 page 2 */
+#define        E1000_SCR_RGMII_POWER_UP        0x0008
+
+/* 88E1116, 88E1149 page 3 */
+#define E1000_SCR_LED_STAT0_MASK       0x000F
+#define E1000_SCR_LED_STAT1_MASK       0x00F0
+#define E1000_SCR_LED_INIT_MASK                0x0F00
+#define E1000_SCR_LED_LOS_MASK         0xF000
+#define E1000_SCR_LED_STAT0(x)         ((x) & E1000_SCR_LED_STAT0_MASK)
+#define E1000_SCR_LED_STAT1(x)         ((x) & E1000_SCR_LED_STAT1_MASK)
+#define E1000_SCR_LED_INIT(x)          ((x) & E1000_SCR_LED_INIT_MASK)
+#define E1000_SCR_LED_LOS(x)           ((x) & E1000_SCR_LED_LOS_MASK)
+
+#define E1000_SSR                      0x11    /* special status register */
+#define E1000_SSR_JABBER               0x0001
+#define E1000_SSR_REV_POLARITY         0x0002
+#define E1000_SSR_MDIX                 0x0020
+#define E1000_SSR_LINK                 0x0400
+#define E1000_SSR_SPD_DPLX_RESOLVED    0x0800
+#define E1000_SSR_PAGE_RCVD            0x1000
+#define E1000_SSR_DUPLEX               0x2000
+#define E1000_SSR_SPEED                        0xC000
+#define E1000_SSR_10MBS                        0x0000
+#define E1000_SSR_100MBS               0x4000
+#define E1000_SSR_1000MBS              0x8000
+



Home | Main Index | Thread Index | Old Index