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[src/trunk]: src/sys/arch/arm/imx add more register definitions.
details: https://anonhg.NetBSD.org/src/rev/a528a8e41854
branches: trunk
changeset: 348391:a528a8e41854
user: ryo <ryo%NetBSD.org@localhost>
date: Mon Oct 17 09:21:51 2016 +0000
description:
add more register definitions.
diffstat:
sys/arch/arm/imx/imx7_ccmreg.h | 6 +-
sys/arch/arm/imx/imx7_gpcreg.h | 5 +-
sys/arch/arm/imx/imx7_rdcreg.h | 643 +++++++++++++++++++++++++++++++++++++++++
sys/arch/arm/imx/imx7_srcreg.h | 3 +-
4 files changed, 654 insertions(+), 3 deletions(-)
diffs (truncated from 710 to 300 lines):
diff -r 102b22f25016 -r a528a8e41854 sys/arch/arm/imx/imx7_ccmreg.h
--- a/sys/arch/arm/imx/imx7_ccmreg.h Mon Oct 17 06:26:37 2016 +0000
+++ b/sys/arch/arm/imx/imx7_ccmreg.h Mon Oct 17 09:21:51 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx7_ccmreg.h,v 1.1 2016/05/17 06:44:45 ryo Exp $ */
+/* $NetBSD: imx7_ccmreg.h,v 1.2 2016/10/17 09:21:51 ryo Exp $ */
/*
* Copyright (c) 2015 Internet Initiative Japan, Inc.
@@ -974,6 +974,10 @@
#define CCM_CCGR190_TOG 0x00004bec
/* CCGR mapping */
+#define CCM_CCGR_M4 CCM_CCGR1
+#define CCM_CCGR_M4_SET (CCM_CCGR_M4 + 4)
+#define CCM_CCGR_M4_CLR (CCM_CCGR_M4 + 8)
+#define CCM_CCGR_M4_TOG (CCM_CCGR_M4 + 12)
#define CCM_CCGR_SIM_MAIN CCM_CCGR4
#define CCM_CCGR_SIM_MAIN_SET (CCM_CCGR_SIM_MAIN + 4)
#define CCM_CCGR_SIM_MAIN_CLR (CCM_CCGR_SIM_MAIN + 8)
diff -r 102b22f25016 -r a528a8e41854 sys/arch/arm/imx/imx7_gpcreg.h
--- a/sys/arch/arm/imx/imx7_gpcreg.h Mon Oct 17 06:26:37 2016 +0000
+++ b/sys/arch/arm/imx/imx7_gpcreg.h Mon Oct 17 09:21:51 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx7_gpcreg.h,v 1.1 2016/05/17 06:44:45 ryo Exp $ */
+/* $NetBSD: imx7_gpcreg.h,v 1.2 2016/10/17 09:21:51 ryo Exp $ */
/*
* Copyright (c) 2015 Internet Initiative Japan, Inc.
@@ -59,6 +59,8 @@
#define GPC_PGC_ACK_SEL_A7_A7_PGC_PUP_ACK __BIT(31)
#define GPC_PGC_ACK_SEL_A7_A7_PGC_PDN_ACK __BIT(15)
#define GPC_PGC_ACK_SEL_M4 0x00000028
+#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK __BIT(31)
+#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK __BIT(15)
#define GPC_MISC 0x0000002c
#define GPC_IMR1_CORE0_A7 0x00000030
#define GPC_IMR2_CORE0_A7 0x00000034
@@ -92,6 +94,7 @@
#define GPC_SLT9_CFG 0x000000d4
#define GPC_PGC_CPU_MAPPING 0x000000ec
#define GPC_PGC_CPU_MAPPING_FASTMEGA_A7_DOMAIN __BIT(0)
+#define GPC_PGC_CPU_MAPPING_FASTMEGA_M4_DOMAIN __BIT(8)
#define GPC_CPU_PGC_SW_PUP_REQ 0x000000f0
#define GPC_PU_PGC_SW_PUP_REQ 0x000000f8
#define GPC_CPU_PGC_SW_PDN_REQ 0x000000fc
diff -r 102b22f25016 -r a528a8e41854 sys/arch/arm/imx/imx7_rdcreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx7_rdcreg.h Mon Oct 17 09:21:51 2016 +0000
@@ -0,0 +1,643 @@
+/* $NetBSD: imx7_rdcreg.h,v 1.1 2016/10/17 09:21:51 ryo Exp $ */
+
+/*
+ * Copyright (c) 2016 Ryo Shimizu <ryo%nerv.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_IMX_IMX7_RDCREG_H_
+#define _ARM_IMX_IMX7_RDCREG_H_
+
+#include <sys/cdefs.h>
+
+/*
+ * Resource Domain Controller Module (AIPS1_RDC_BASE:0x303d0000)
+ */
+#define RDC_VIR 0x00000000
+#define RDC_STAT 0x00000024
+#define RDC_INTCTRL 0x00000028
+#define RDC_INTSTAT 0x0000002c
+
+/* Master Domain Assignment */
+#define RDC_MDA0 0x00000200
+#define RDC_MDA1 0x00000204
+#define RDC_MDA2 0x00000208
+#define RDC_MDA3 0x0000020c
+#define RDC_MDA4 0x00000210
+#define RDC_MDA5 0x00000214
+#define RDC_MDA6 0x00000218
+#define RDC_MDA7 0x0000021c
+#define RDC_MDA8 0x00000220
+#define RDC_MDA9 0x00000224
+#define RDC_MDA10 0x00000228
+#define RDC_MDA11 0x0000022c
+#define RDC_MDA12 0x00000230
+#define RDC_MDA13 0x00000234
+#define RDC_MDA14 0x00000238
+#define RDC_MDA15 0x0000023c
+#define RDC_MDA16 0x00000240
+#define RDC_MDA17 0x00000244
+#define RDC_MDA18 0x00000248
+#define RDC_MDA19 0x0000024c
+#define RDC_MDA20 0x00000250
+#define RDC_MDA21 0x00000254
+#define RDC_MDA22 0x00000258
+#define RDC_MDA23 0x0000025c
+#define RDC_MDA24 0x00000260
+#define RDC_MDA25 0x00000264
+#define RDC_MDA26 0x00000268
+
+#define RDC_MDA_A7_CORE_0 RDC_MDA0
+#define RDC_MDA_A7_CORE_1 RDC_MDA0
+#define RDC_MDA_M4_CORE RDC_MDA1
+#define RDC_MDA_PCIE_CTRL RDC_MDA2
+#define RDC_MDA_SCI RDC_MDA3
+#define RDC_MDA_EPDC RDC_MDA4
+#define RDC_MDA_LCDIF RDC_MDA5
+#define RDC_MDA_DISPLAY_PORT RDC_MDA6
+#define RDC_MDA_PXP RDC_MDA7
+#define RDC_MDA_CORESIGHT RDC_MDA8
+#define RDC_MDA_DAP RDC_MDA9
+#define RDC_MDA_CAAM RDC_MDA10
+#define RDC_MDA_SDMA_PERIPHERAL_DMA_PORT RDC_MDA11
+#define RDC_MDA_SDMA_BURST_DMA_PORT RDC_MDA12
+#define RDC_MDA_APBHDMA RDC_MDA13
+#define RDC_MDA_RAWNAND RDC_MDA14
+#define RDC_MDA_USDHC1 RDC_MDA15
+#define RDC_MDA_USDHC2 RDC_MDA16
+#define RDC_MDA_USDHC3 RDC_MDA17
+#define RDC_MDA_NC18 RDC_MDA18
+#define RDC_MDA_USB RDC_MDA19
+#define RDC_MDA_NC20 RDC_MDA20
+#define RDC_MDA_TESTPORT RDC_MDA21
+#define RDC_MDA_ENET1_TX RDC_MDA22
+#define RDC_MDA_ENET1_RX RDC_MDA23
+#define RDC_MDA_ENET2_TX RDC_MDA24
+#define RDC_MDA_ENET2_RX RDC_MDA25
+#define RDC_MDA_SDMA_PORT RDC_MDA26
+
+/* RDC Peripheral Mapping */
+#define RDC_PDAP0 0x00000400
+#define RDC_PDAP1 0x00000404
+#define RDC_PDAP2 0x00000408
+#define RDC_PDAP3 0x0000040c
+#define RDC_PDAP4 0x00000410
+#define RDC_PDAP5 0x00000414
+#define RDC_PDAP6 0x00000418
+#define RDC_PDAP7 0x0000041c
+#define RDC_PDAP8 0x00000420
+#define RDC_PDAP9 0x00000424
+#define RDC_PDAP10 0x00000428
+#define RDC_PDAP11 0x0000042c
+#define RDC_PDAP12 0x00000430
+#define RDC_PDAP13 0x00000434
+#define RDC_PDAP14 0x00000438
+#define RDC_PDAP15 0x0000043c
+#define RDC_PDAP16 0x00000440
+#define RDC_PDAP17 0x00000444
+#define RDC_PDAP18 0x00000448
+#define RDC_PDAP19 0x0000044c
+#define RDC_PDAP20 0x00000450
+#define RDC_PDAP21 0x00000454
+#define RDC_PDAP22 0x00000458
+#define RDC_PDAP23 0x0000045c
+#define RDC_PDAP24 0x00000460
+#define RDC_PDAP25 0x00000464
+#define RDC_PDAP26 0x00000468
+#define RDC_PDAP27 0x0000046c
+#define RDC_PDAP28 0x00000470
+#define RDC_PDAP29 0x00000474
+#define RDC_PDAP30 0x00000478
+#define RDC_PDAP31 0x0000047c
+#define RDC_PDAP32 0x00000480
+#define RDC_PDAP33 0x00000484
+#define RDC_PDAP34 0x00000488
+#define RDC_PDAP35 0x0000048c
+#define RDC_PDAP36 0x00000490
+#define RDC_PDAP37 0x00000494
+#define RDC_PDAP38 0x00000498
+#define RDC_PDAP39 0x0000049c
+#define RDC_PDAP40 0x000004a0
+#define RDC_PDAP41 0x000004a4
+#define RDC_PDAP42 0x000004a8
+#define RDC_PDAP43 0x000004ac
+#define RDC_PDAP44 0x000004b0
+#define RDC_PDAP45 0x000004b4
+#define RDC_PDAP46 0x000004b8
+#define RDC_PDAP47 0x000004bc
+#define RDC_PDAP48 0x000004c0
+#define RDC_PDAP49 0x000004c4
+#define RDC_PDAP50 0x000004c8
+#define RDC_PDAP51 0x000004cc
+#define RDC_PDAP52 0x000004d0
+#define RDC_PDAP53 0x000004d4
+#define RDC_PDAP54 0x000004d8
+#define RDC_PDAP55 0x000004dc
+#define RDC_PDAP56 0x000004e0
+#define RDC_PDAP57 0x000004e4
+#define RDC_PDAP58 0x000004e8
+#define RDC_PDAP59 0x000004ec
+#define RDC_PDAP60 0x000004f0
+#define RDC_PDAP61 0x000004f4
+#define RDC_PDAP62 0x000004f8
+#define RDC_PDAP63 0x000004fc
+#define RDC_PDAP64 0x00000500
+#define RDC_PDAP65 0x00000504
+#define RDC_PDAP66 0x00000508
+#define RDC_PDAP67 0x0000050c
+#define RDC_PDAP68 0x00000510
+#define RDC_PDAP69 0x00000514
+#define RDC_PDAP70 0x00000518
+#define RDC_PDAP71 0x0000051c
+#define RDC_PDAP72 0x00000520
+#define RDC_PDAP73 0x00000524
+#define RDC_PDAP74 0x00000528
+#define RDC_PDAP75 0x0000052c
+#define RDC_PDAP76 0x00000530
+#define RDC_PDAP77 0x00000534
+#define RDC_PDAP78 0x00000538
+#define RDC_PDAP79 0x0000053c
+#define RDC_PDAP80 0x00000540
+#define RDC_PDAP81 0x00000544
+#define RDC_PDAP82 0x00000548
+#define RDC_PDAP83 0x0000054c
+#define RDC_PDAP84 0x00000550
+#define RDC_PDAP85 0x00000554
+#define RDC_PDAP86 0x00000558
+#define RDC_PDAP87 0x0000055c
+#define RDC_PDAP88 0x00000560
+#define RDC_PDAP89 0x00000564
+#define RDC_PDAP90 0x00000568
+#define RDC_PDAP91 0x0000056c
+#define RDC_PDAP92 0x00000570
+#define RDC_PDAP93 0x00000574
+#define RDC_PDAP94 0x00000578
+#define RDC_PDAP95 0x0000057c
+#define RDC_PDAP96 0x00000580
+#define RDC_PDAP97 0x00000584
+#define RDC_PDAP98 0x00000588
+#define RDC_PDAP99 0x0000058c
+#define RDC_PDAP100 0x00000590
+#define RDC_PDAP101 0x00000594
+#define RDC_PDAP102 0x00000598
+#define RDC_PDAP103 0x0000059c
+#define RDC_PDAP104 0x000005a0
+#define RDC_PDAP105 0x000005a4
+#define RDC_PDAP106 0x000005a8
+#define RDC_PDAP107 0x000005ac
+#define RDC_PDAP108 0x000005b0
+#define RDC_PDAP109 0x000005b4
+#define RDC_PDAP110 0x000005b8
+#define RDC_PDAP111 0x000005bc
+#define RDC_PDAP112 0x000005c0
+#define RDC_PDAP113 0x000005c4
+#define RDC_PDAP114 0x000005c8
+#define RDC_PDAP115 0x000005cc
+#define RDC_PDAP116 0x000005d0
+#define RDC_PDAP117 0x000005d4
+
+#define RDC_PDAP_GPIO1 RDC_PDAP0
+#define RDC_PDAP_GPIO2 RDC_PDAP1
+#define RDC_PDAP_GPIO3 RDC_PDAP2
+#define RDC_PDAP_GPIO4 RDC_PDAP3
+#define RDC_PDAP_GPIO5 RDC_PDAP4
+#define RDC_PDAP_GPIO6 RDC_PDAP5
+#define RDC_PDAP_GPIO7 RDC_PDAP6
+#define RDC_PDAP_IOMUXC_LPSR_GPR RDC_PDAP7
+#define RDC_PDAP_WDOG1 RDC_PDAP8
+#define RDC_PDAP_WDOG2 RDC_PDAP9
+#define RDC_PDAP_WDOG3 RDC_PDAP10
+#define RDC_PDAP_WDOG4 RDC_PDAP11
+#define RDC_PDAP_IOMUXC_LPSR RDC_PDAP12
+#define RDC_PDAP_GPT1 RDC_PDAP13
+#define RDC_PDAP_GPT2 RDC_PDAP14
+#define RDC_PDAP_GPT3 RDC_PDAP15
+#define RDC_PDAP_GPT4 RDC_PDAP16
+#define RDC_PDAP_ROMCP RDC_PDAP17
+#define RDC_PDAP_KPP RDC_PDAP18
+#define RDC_PDAP_IOMUXC RDC_PDAP19
+#define RDC_PDAP_IOMUXC_GPR RDC_PDAP20
+#define RDC_PDAP_OCOTP_CTRL RDC_PDAP21
+#define RDC_PDAP_ANATOP_DIG RDC_PDAP22
+#define RDC_PDAP_SNVS_HP RDC_PDAP23
+#define RDC_PDAP_CCM RDC_PDAP24
+#define RDC_PDAP_SRC RDC_PDAP25
+#define RDC_PDAP_GPC RDC_PDAP26
+#define RDC_PDAP_SEMAPHORE1 RDC_PDAP27
+#define RDC_PDAP_SEMAPHORE2 RDC_PDAP28
+#define RDC_PDAP_RDC RDC_PDAP29
+#define RDC_PDAP_CSU RDC_PDAP30
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