[src/trunk]: src/sys/arch/mips/ingenic add some clock divider registers

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/37740075f586
branches:  trunk
changeset: 338325:37740075f586
user:      macallan <macallan%NetBSD.org@localhost>
date:      Mon May 18 15:03:16 2015 +0000

description:
add some clock divider registers

diffstat:

 sys/arch/mips/ingenic/ingenic_regs.h |  24 +++++++++++++++++++++++-
 1 files changed, 23 insertions(+), 1 deletions(-)

diffs (45 lines):

diff -r 29423e3c34e5 -r 37740075f586 sys/arch/mips/ingenic/ingenic_regs.h
--- a/sys/arch/mips/ingenic/ingenic_regs.h      Mon May 18 14:41:41 2015 +0000
+++ b/sys/arch/mips/ingenic/ingenic_regs.h      Mon May 18 15:03:16 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ingenic_regs.h,v 1.17 2015/05/04 12:16:24 macallan Exp $ */
+/*     $NetBSD: ingenic_regs.h,v 1.18 2015/05/18 15:03:16 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -269,6 +269,7 @@
        #define PCR_TXHSXVTUNE          0x00000030
        #define PCR_TXVREFTUNE          0x0000000f
 #define JZ_USBRDT      0x10000040      /* Reset Detect Timer Register */
+#define JZ_USBVBFIL    0x10000044
 #define JZ_USBPCR1     0x10000048
        #define PCR_SYNOPSYS    0x10000000      /* Mentor mode otherwise */
        #define PCR_REFCLK_CORE 0x0c000000
@@ -306,6 +307,27 @@
 #define JZ_SPCR1       0x100000bc
 #define JZ_SRBC                0x100000c4      /* Soft Reset & Bus Control */
 
+/* clock divider registers */
+#define JZ_MSC0CDR     0x10000068
+       #define MSCCDR_SCLK_A   0x40000000
+       #define MSCCDR_MPLL     0x80000000
+       #define MSCCDR_CE       0x20000000
+       #define MSCCDR_BUSY     0x10000000
+       #define MSCCDR_STOP     0x08000000
+       #define MSCCDR_PHASE    0x00008000      /* 0 - 90deg phase, 1 - 180 */
+       #define MSCCDR_DIV_M    0x000000ff      /* src / ((div + 1) * 2) */
+#define JZ_UHCCDR      0x1000006c      /* UHC Clock Divider Register */
+       #define UHCCDR_SCLK_A   0x00000000
+       #define UHCCDR_MPLL     0x40000000
+       #define UHCCDR_EPLL     0x80000000
+       #define UHCCDR_OTG_PHY  0xc0000000
+       #define UHCCDR_CE       0x20000000
+       #define UHCCDR_BUSY     0x10000000
+       #define UHCCDR_STOP     0x08000000
+       #define UHCCDR_DIV_M    0x000000ff
+#define JZ_MSC1CDR     0x100000a4
+#define JZ_MSC2CDR     0x100000a8
+
 /* interrupt controller */
 #define JZ_ICSR0       0x10001000      /* raw IRQ line status */
 #define JZ_ICMR0       0x10001004      /* IRQ mask, 1 masks IRQ */