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[src/trunk]: src/sys/arch Preliminary support for P1023.



details:   https://anonhg.NetBSD.org/src/rev/86ad937d106a
branches:  trunk
changeset: 335138:86ad937d106a
user:      nonaka <nonaka%NetBSD.org@localhost>
date:      Sat Dec 27 16:19:33 2014 +0000

description:
Preliminary support for P1023.

diffstat:

 sys/arch/evbppc/conf/files.mpc85xx          |   4 +-
 sys/arch/evbppc/mpc85xx/machdep.c           |  44 ++++++++++++++++---------
 sys/arch/powerpc/booke/dev/pq3gpio.c        |  49 ++++++++++++++++++++++++++--
 sys/arch/powerpc/booke/e500_intr.c          |  33 ++++++++++++++++++-
 sys/arch/powerpc/booke/pci/pq3pci.c         |  24 +++++++++++++-
 sys/arch/powerpc/include/booke/e500reg.h    |  12 ++++++-
 sys/arch/powerpc/include/booke/openpicreg.h |  46 +++++++++++++++++++++++---
 7 files changed, 179 insertions(+), 33 deletions(-)

diffs (truncated from 473 to 300 lines):

diff -r e8c7850b67b4 -r 86ad937d106a sys/arch/evbppc/conf/files.mpc85xx
--- a/sys/arch/evbppc/conf/files.mpc85xx        Sat Dec 27 16:19:24 2014 +0000
+++ b/sys/arch/evbppc/conf/files.mpc85xx        Sat Dec 27 16:19:33 2014 +0000
@@ -1,9 +1,9 @@
-#      $NetBSD: files.mpc85xx,v 1.9 2012/07/15 08:44:56 matt Exp $
+#      $NetBSD: files.mpc85xx,v 1.10 2014/12/27 16:19:33 nonaka Exp $
 #
 # mpc85xx-specific configuration info
 
 defflag        opt_mpc85xx.h   MPC8536 MPC8544 MPC8548 MPC8555 MPC8568 MPC8572
-                       P1025 P2020 CADMUS PIXIS E500_WDOG_STACK
+                       P1023 P1025 P2020 CADMUS PIXIS E500_WDOG_STACK
 defparam opt_mpc85xx.h SYS_CLK MEMSIZE
 
 file   arch/evbppc/mpc85xx/autoconf.c
diff -r e8c7850b67b4 -r 86ad937d106a sys/arch/evbppc/mpc85xx/machdep.c
--- a/sys/arch/evbppc/mpc85xx/machdep.c Sat Dec 27 16:19:24 2014 +0000
+++ b/sys/arch/evbppc/mpc85xx/machdep.c Sat Dec 27 16:19:33 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: machdep.c,v 1.36 2014/12/19 04:31:41 nonaka Exp $      */
+/*     $NetBSD: machdep.c,v 1.37 2014/12/27 16:19:33 nonaka Exp $      */
 /*-
  * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -207,14 +207,15 @@
 static const struct cpunode_locators mpc8548_cpunode_locs[] = {
        { "cpu", 0, 0, 0, 0, { 0 }, 0,  /* not a real device */
                { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
-                 SVR_P1025v1 >> 16 } },
-#if defined(MPC8572) || defined(P2020) || defined(P1025)
+                 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
+#if defined(MPC8572) || defined(P2020) || defined(P1025) \
+    || defined(P1023)
        { "cpu", 0, 0, 1, 0, { 0 }, 0,  /* not a real device */
                { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
-                 SVR_P1025v1 >> 16 } },
+                 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
        { "cpu", 0, 0, 2, 0, { 0 }, 0,  /* not a real device */
                { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
-                 SVR_P1025v1 >> 16 } },
+                 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
 #endif
        { "wdog" },     /* not a real device */
        { "duart", DUART1_BASE, 2*DUART_SIZE, 0,
@@ -223,7 +224,7 @@
        { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1,
                3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR },
                1 + ilog2(DEVDISR_TSEC1),
-               { 0xffff, SVR_P1025v1 >> 16 } },
+               { 0xffff, SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
 #if defined(P1025)
        { "mdio", ETSEC1_BASE, ETSEC_SIZE, 1,
                0, { },
@@ -366,30 +367,33 @@
                1 + ilog2(DEVDISR_PCI2),
                { SVR_MPC8548v1 >> 16 }, },
 #endif
-#if defined(MPC8572) || defined(P1025) || defined(P2020)
+#if defined(MPC8572) || defined(P1025) || defined(P2020) \
+    || defined(P1023)
        { "pcie", PCIE1_BASE, PCI_SIZE, 1,
                1, { ISOURCE_PCIEX },
                1 + ilog2(DEVDISR_PCIE),
                { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
-                 SVR_P1025v1 >> 16 } },
+                 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
        { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2,
                1, { ISOURCE_PCIEX2 },
                1 + ilog2(DEVDISR_PCIE2),
                { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
-                 SVR_P1025v1 >> 16 } },
+                 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
 #endif
-#if defined(MPC8572) || defined(P2020)
+#if defined(MPC8572) || defined(P2020) || defined(_P1023)
        { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3,
                1, { ISOURCE_PCIEX3_MPC8572 },
                1 + ilog2(DEVDISR_PCIE3),
-               { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, } },
+               { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
+                 SVR_P1023v1 >> 16 } },
 #endif
-#if defined(MPC8536) || defined(P1025) || defined(P2020)
+#if defined(MPC8536) || defined(P1025) || defined(P2020) \
+    || defined(P1023)
        { "ehci", USB1_BASE, USB_SIZE, 1,
                1, { ISOURCE_USB1 },
                1 + ilog2(DEVDISR_USB1),
                { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16,
-                 SVR_P1025v1 >> 16 } },
+                 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } },
 #endif
 #ifdef MPC8536
        { "ehci", USB2_BASE, USB_SIZE, 2,
@@ -417,11 +421,14 @@
                1 + ilog2(DEVDISR_ESDHC_12),
                { SVR_MPC8536v1 >> 16 }, },
 #endif
-#if defined(P1025) || defined(P2020)
+#if defined(P1025) || defined(P2020) || defined(P1023)
        { "spi", SPI_BASE, SPI_SIZE, 0,
                1, { ISOURCE_SPI },
                1 + ilog2(DEVDISR_SPI_28),
-               { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, },
+               { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16,
+                 SVR_P1023v1 >> 16 }, },
+#endif
+#if defined(P1025) || defined(P2020)
        { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0,
                1, { ISOURCE_ESDHC },
                1 + ilog2(DEVDISR_ESDHC_10),
@@ -681,6 +688,7 @@
        case SVR_MPC8541v1 >> 16:       return SVR_MPC8555v1 >> 16;
        case SVR_P2010v2 >> 16:         return SVR_P2020v2 >> 16;
        case SVR_P1016v1 >> 16:         return SVR_P1025v1 >> 16;
+       case SVR_P1017v1 >> 16:         return SVR_P1023v1 >> 16;
        default:                        return svr;
        }
 }
@@ -705,6 +713,8 @@
        case SVR_P2020v2 >> 8: return "P2020";
        case SVR_P2010v2 >> 8: return "P2010";
        case SVR_P1016v1 >> 8: return "P1016";
+       case SVR_P1017v1 >> 8: return "P1017";
+       case SVR_P1023v1 >> 8: return "P1023";
        case SVR_P1025v1 >> 8: return "P1025";
        default:
                panic("%s: unknown SVR %#x", __func__, svr);
@@ -1490,11 +1500,13 @@
                break;
 #endif
 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \
-    || defined(P1025) || defined(P2020)
+    || defined(P1025) || defined(P2020) || defined(P1023)
        case SVR_MPC8536v1 >> 16:
        case SVR_MPC8544v1 >> 16:
        case SVR_MPC8572v1 >> 16:
        case SVR_P1016v1 >> 16:
+       case SVR_P1017v1 >> 16:
+       case SVR_P1023v1 >> 16:
        case SVR_P2010v2 >> 16:
        case SVR_P2020v2 >> 16:
                mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL,
diff -r e8c7850b67b4 -r 86ad937d106a sys/arch/powerpc/booke/dev/pq3gpio.c
--- a/sys/arch/powerpc/booke/dev/pq3gpio.c      Sat Dec 27 16:19:24 2014 +0000
+++ b/sys/arch/powerpc/booke/dev/pq3gpio.c      Sat Dec 27 16:19:33 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pq3gpio.c,v 1.10 2014/12/20 18:03:17 nonaka Exp $      */
+/*     $NetBSD: pq3gpio.c,v 1.11 2014/12/27 16:19:33 nonaka Exp $      */
 /*-
  * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -41,7 +41,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.10 2014/12/20 18:03:17 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.11 2014/12/27 16:19:33 nonaka Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -161,9 +161,9 @@
 }
 #endif
 
-#if defined(MPC8536) || defined(P2020)
+#if defined(MPC8536) || defined(P2020) || defined(P1023)
 /*
- * MPC8536 / P20x0 have controllable input/output pins
+ * MPC8536 / P20x0 / P1023 have controllable input/output pins
  */
 static void
 pq3gpio_pin_ctl(void *v, int num, int ctl)
@@ -465,6 +465,43 @@
 }
 #endif /* P2020 */
 
+#ifdef P1023
+static void
+pq3gpio_p1023_attach(device_t self, bus_space_tag_t bst,
+       bus_space_handle_t bsh, u_int svr)
+{
+       static const uint32_t gpio2pmuxcr2_map[][3] = {
+               { __PPCBITS( 0, 1), __PPCBITS( 0, 1), 0 },      /* GPIO_1 */
+               { __PPCBIT(2),      __PPCBITS( 2, 3), 0 },      /* GPUO_2 */
+               { __PPCBITS( 4, 5), __PPCBITS( 4, 5), 0 },      /* GPUO_3 */
+               { __PPCBITS( 6, 7), __PPCBITS( 6, 7), 0 },      /* GPUO_4 */
+               { __PPCBITS( 8, 9), __PPCBITS( 8, 9), 0 },      /* GPUO_5 */
+               { __PPCBITS(10,11), __PPCBITS(10,11), 0 },      /* GPUO_6 */
+               { __PPCBITS(12,13), __PPCBITS(12,13), 0 },      /* GPUO_7 */
+               { __PPCBITS(14,15), __PPCBITS(14,15), 0 },      /* GPUO_8 */
+               { __PPCBIT(3),      __PPCBITS(18,19), 0 },      /* GPUO_9 */
+       };
+
+       uint32_t pinmask = 0xffff0000;  /* assume all bits are valid */
+       size_t pincnt = 16;
+       const uint32_t pmuxcr2 = cpu_read_4(GLOBAL_BASE + PMUXCR2);
+       for (size_t i = 0; i < __arraycount(gpio2pmuxcr2_map); i++) {
+               const uint32_t *map = gpio2pmuxcr2_map[i];
+               if ((pmuxcr2 & map[1]) != map[2]) {
+                       pinmask &= ~map[0];
+                       pincnt--;
+               }
+       }
+
+       /*
+        * Create GPIO pin groups
+        */
+       aprint_normal_dev(self, "%zu input/output/opendrain pins\n", pincnt);
+       pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask,
+           GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN, pq3gpio_pin_ctl);
+}
+#endif /* P1023 */
+
 static const struct pq3gpio_svr_info {
        uint16_t si_svr;
        void (*si_attach)(device_t, bus_space_tag_t, bus_space_handle_t, u_int);
@@ -495,6 +532,10 @@
        { SVR_P2020v2 >> 16, pq3gpio_p20x0_attach,
            GPIO_BASE, GPIO_SIZE },
 #endif
+#ifdef P1023
+       { SVR_P1023v1 >> 16, pq3gpio_p1023_attach,
+           GPIO_BASE, GPIO_SIZE },
+#endif
 };
 
 void
diff -r e8c7850b67b4 -r 86ad937d106a sys/arch/powerpc/booke/e500_intr.c
--- a/sys/arch/powerpc/booke/e500_intr.c        Sat Dec 27 16:19:24 2014 +0000
+++ b/sys/arch/powerpc/booke/e500_intr.c        Sat Dec 27 16:19:33 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: e500_intr.c,v 1.27 2014/12/20 17:55:07 nonaka Exp $    */
+/*     $NetBSD: e500_intr.c,v 1.28 2014/12/27 16:19:33 nonaka Exp $    */
 /*-
  * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -39,7 +39,7 @@
 #define __INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.27 2014/12/20 17:55:07 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.28 2014/12/27 16:19:33 nonaka Exp $");
 
 #include <sys/param.h>
 #include <sys/proc.h>
@@ -360,6 +360,29 @@
 INTR_INFO_DECL(p20x0, P20x0);
 #endif
 
+#ifdef P1023
+#define        p1023_external_intr_names       default_external_intr_names
+const struct e500_intr_name p1023_onchip_intr_names[] = {
+       { ISOURCE_FMAN,            "fman" },
+       { ISOURCE_MDIO,            "mdio" },
+       { ISOURCE_QMAN0,           "qman0" },
+       { ISOURCE_BMAN0,           "bman0" },
+       { ISOURCE_QMAN1,           "qman1" },
+       { ISOURCE_BMAN1,           "bman1" },
+       { ISOURCE_QMAN2,           "qman2" },
+       { ISOURCE_BMAN2,           "bman2" },
+       { ISOURCE_SECURITY2_P1023, "sec2" },
+       { ISOURCE_SEC_GENERAL,     "sec-general" },
+       { ISOURCE_DMA2_CHAN1,      "dma2-chan1" },
+       { ISOURCE_DMA2_CHAN2,      "dma2-chan2" },
+       { ISOURCE_DMA2_CHAN3,      "dma2-chan3" },
+       { ISOURCE_DMA2_CHAN4,      "dma2-chan4" },
+       { 0, "" },
+};
+
+INTR_INFO_DECL(p1023, P1023);
+#endif
+
 static const char ist_names[][12] = {
        [IST_NONE] = "none",
        [IST_EDGE] = "edge",
@@ -1048,6 +1071,12 @@
                *ii = mpc8572_intr_info;
                break;
 #endif
+#ifdef P1023
+       case SVR_P1017v1 >> 16:
+       case SVR_P1023v1 >> 16:
+               *ii = p1023_intr_info;
+               break;
+#endif
 #ifdef P1025
        case SVR_P1016v1 >> 16:
        case SVR_P1025v1 >> 16:
diff -r e8c7850b67b4 -r 86ad937d106a sys/arch/powerpc/booke/pci/pq3pci.c
--- a/sys/arch/powerpc/booke/pci/pq3pci.c       Sat Dec 27 16:19:24 2014 +0000
+++ b/sys/arch/powerpc/booke/pci/pq3pci.c       Sat Dec 27 16:19:33 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pq3pci.c,v 1.19 2014/12/20 18:03:17 nonaka Exp $       */
+/*     $NetBSD: pq3pci.c,v 1.20 2014/12/27 16:19:33 nonaka Exp $       */
 /*-
  * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -44,7 +44,7 @@
 



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