[src/trunk]: src/sys/arch/mips/ingenic even more registers

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a3d82c8ef1b3
branches:  trunk
changeset: 335087:a3d82c8ef1b3
user:      macallan <macallan%NetBSD.org@localhost>
date:      Thu Dec 25 05:10:00 2014 +0000

description:
even more registers

diffstat:

 sys/arch/mips/ingenic/ingenic_regs.h |  7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diffs (28 lines):

diff -r 33dd2d98f4b3 -r a3d82c8ef1b3 sys/arch/mips/ingenic/ingenic_regs.h
--- a/sys/arch/mips/ingenic/ingenic_regs.h      Thu Dec 25 01:38:28 2014 +0000
+++ b/sys/arch/mips/ingenic/ingenic_regs.h      Thu Dec 25 05:10:00 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ingenic_regs.h,v 1.5 2014/12/23 18:48:52 macallan Exp $ */
+/*     $NetBSD: ingenic_regs.h,v 1.6 2014/12/25 05:10:00 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -198,7 +198,7 @@
        #define PCR_TXPREEMPHTUNE       0x00000040
        #define PCR_TXHSXVTUNE          0x00000030
        #define PCR_TXVREFTUNE          0x0000000f
-
+#define JZ_USBRDT      0x10000040      /* Reset Detect Timer Register */
 #define JZ_USBPCR1     0x10000048
        #define PCR_SYNOPSYS    0x10000000      /* Mentor mode otherwise */
        #define PCR_REFCLK_CORE 0x0c000000
@@ -222,7 +222,8 @@
        #define PCR_TXHSXVTUNE1 0x00000060      /* dp/dm voltage adj. */
        #define PCR_TXVREFTUNE1 0x00000017      /* HS DC voltage adj. */
        #define PCR_TXRISETUNE1 0x00000001      /* risa/fall wave adj. */
-       
+
+#define JZ_UHCCDR      0x1000006c      /* UHC Clock Divider Register */
 #define JZ_SPCR0       0x100000b8      /* SRAM Power Control Registers */
 #define JZ_SPCR1       0x100000bc
 #define JZ_SRBC                0x100000c4      /* Soft Reset & Bus Control */