[src/trunk]: src/sys/arch/arm/allwinner Remove unneeded delays. for ACHI por...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/6697d993fc32
branches:  trunk
changeset: 326977:6697d993fc32
user:      matt <matt%NetBSD.org@localhost>
date:      Mon Feb 24 16:40:29 2014 +0000

description:
Remove unneeded delays.  for ACHI port reg, act like ahcisatareg.h
(e.g. AHCI_P_AWIN_DMA(p))

diffstat:

 sys/arch/arm/allwinner/awin_ahcisata.c |  33 ++++++++++++++-------------------
 sys/arch/arm/allwinner/awin_reg.h      |   2 +-
 2 files changed, 15 insertions(+), 20 deletions(-)

diffs (113 lines):

diff -r 83e80770eec8 -r 6697d993fc32 sys/arch/arm/allwinner/awin_ahcisata.c
--- a/sys/arch/arm/allwinner/awin_ahcisata.c    Mon Feb 24 16:15:43 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_ahcisata.c    Mon Feb 24 16:40:29 2014 +0000
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: awin_ahcisata.c,v 1.10 2014/02/24 15:47:43 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_ahcisata.c,v 1.11 2014/02/24 16:40:29 matt Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -86,38 +86,34 @@
         */
        delay(5000);
        bus_space_write_4(bst, bsh, AWIN_AHCI_RWCR_REG, 0);
-       delay(10);
 
        awin_reg_set_clear(bst, bsh, AWIN_AHCI_PHYCS1R_REG, __BIT(19), 0);
-       delay(10);
+
        awin_reg_set_clear(bst, bsh, AWIN_AHCI_PHYCS0R_REG,
            __BIT(26)|__BIT(24)|__BIT(23)|__BIT(18),
            __BIT(25));
-       delay(10);
+
        awin_reg_set_clear(bst, bsh, AWIN_AHCI_PHYCS1R_REG,
            __BIT(17)|__BIT(10)|__BIT(9)|__BIT(7),
            __BIT(16)|__BIT(12)|__BIT(11)|__BIT(8)|__BIT(6));
-       delay(10);
+
        awin_reg_set_clear(bst, bsh, AWIN_AHCI_PHYCS1R_REG,
            __BIT(28)|__BIT(15), 0);
-       delay(10);
+
        awin_reg_set_clear(bst, bsh, AWIN_AHCI_PHYCS1R_REG, 0, __BIT(19));
-       delay(10);
 
        awin_reg_set_clear(bst, bsh, AWIN_AHCI_PHYCS0R_REG,
            __BIT(21)|__BIT(20), __BIT(22));
-       delay(10);
+
        awin_reg_set_clear(bst, bsh, AWIN_AHCI_PHYCS2R_REG,
            __BIT(9)|__BIT(8)|__BIT(5), __BIT(7)|__BIT(6));
-       delay(20);
 
-       delay(5000);
+       delay(10);
        awin_reg_set_clear(bst, bsh, AWIN_AHCI_PHYCS0R_REG, __BIT(19), 0);
-       delay(20);
 
        timeout = 1000;
        do {
-               delay(10);
+               delay(1);
                v = bus_space_read_4(bst, bsh, AWIN_AHCI_PHYCS0R_REG);
        } while (--timeout && __SHIFTOUT(v, __BITS(30,28)) != 2);
 
@@ -141,7 +137,7 @@
                            "SATA PHY calibration failed (%#x)\n", v);
                }
        }
-       delay(15000);
+       delay(10);
        bus_space_write_4(bst, bsh, AWIN_AHCI_RWCR_REG, 7);
 }
 
@@ -169,12 +165,12 @@
 static void
 awin_ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp)
 {
-       uint32_t dma;
+       bus_size_t dma_reg = AHCI_P_AWIN_DMA(chp->ch_channel);
 
-       dma = AHCI_READ(sc, 0x100 + AHCI_P_OFFSET(chp->ch_channel) + AWIN_AHCI_DMA_REG);
+       uint32_t dma = AHCI_READ(sc, dma_reg);
        dma &= ~0xff00;
        dma |= 0x4400;
-       AHCI_WRITE(sc, 0x100 + AHCI_P_OFFSET(chp->ch_channel) + AWIN_AHCI_DMA_REG, dma);
+       AHCI_WRITE(sc, dma_reg, dma);
 }
 
 static void
@@ -224,15 +220,14 @@
        /*
         * Establish the interrupt
         */
-       asc->asc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL,
+       asc->asc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_LEVEL,
            ahci_intr, sc);
        if (asc->asc_ih == NULL) {
                aprint_error_dev(self, "failed to establish interrupt %d\n",
                     loc->loc_intr);
                goto fail;
        }
-       aprint_normal_dev(self, "interrupting on irq %d\n",
-            loc->loc_intr);
+       aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
 
        ahci_attach(sc);
 
diff -r 83e80770eec8 -r 6697d993fc32 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Mon Feb 24 16:15:43 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Mon Feb 24 16:40:29 2014 +0000
@@ -562,7 +562,7 @@
 #define AWIN_EMAC_INT_TX1              __BIT(1)
 #define AWIN_EMAC_INT_TX0              __BIT(0)
 
-#define AWIN_AHCI_DMA_REG              0x0070
+#define AHCI_P_AWIN_DMA(p)             (0x170 + AHCI_P_OFFSET(p))
 #define AWIN_AHCI_BISTAFR_REG          0x00A0
 #define AWIN_AHCI_BISTCR_REG           0x00A4
 #define AWIN_AHCI_BISTFCTR_REG         0x00A8