London Open Source Meetup for RISC-V 21/10/19

[Sevan Janiyan <venture37%geeklan.co.uk@localhost>]

This is our quarterly meetup for the London open source community,
focusing on RISC-V, hosted by the BCS Open Source Specialist Group and
the UK Open Source Hardware User Group.

Registration link: https://ossg211019.eventbrite.co.uk/

Note. This meeting is at the new BCS London offices, 25 Copthall Ave,
EC2R 7BP.

At this evening meeting we have three talks on the CHIPS alliance, a
comparative analysis of the RISC-V ecosystem and a look at RISC-V in
education.  The talks will be live streamed and available on afterwards
on the BCS Open Source Specialist Group YouTube channel.


Tea/coffee will be served from 6:00pm, with talks starting at 6:30pm.
Each talk will last 20-30 minutes and include plenty of time for
questions, after which there will be opportunity to network both in the
BCS  and later at the Globe pub round the corner.

We shall be livestreaming and recording the talks for later posting on
YouTube via GoToWebinar.  Please register at:

https://attendee.gotowebinar.com/register/2236026621826907405

After registering, you will receive a confirmation email containing
information about joining the webinar.

*Chips Alliance Project*
Dr Zvonimir Z. Bandić, @zbandic

We have recently launched a CHIPS Alliance project: CHIPS (Common
Hardware for Interfaces, Processors and Systems) Alliance harnesses the
energy of open source collaboration to accelerate hardware development.
The organization was created to host and curate high-quality, open
source hardware design relevant to the design of silicon devices. By
creating a neutral and collaborative environment, CHIPS Alliance intends
to share resources to lower the cost of development and accelerate the
creation of more efficient and innovative chip designs – covering the
span from small IoT devices to large datacenter silicon solutions.

As an independent entity, companies and individuals can work together
and contribute resources to help make open source chips, complex IP
blocks and system-on-a-chip (SoC) design more accessible to the market.

We will describe our initial projects, which are SweRV core – high
performance, 9-stage, dual issue, 32 bit superscalar RISC-V core,
associated instruction set simulator, Universal Verification Methodology
(UVM)-Based Stream Generator Environment for RISC-V Cores, that provides
configurable, highly stressful instruction sequences that can verify
architectural and micro-architectural corner-cases of designs, OmniXtend
cache-coherence over ethernet interconnect protocol, FuseSOC package
manager, Verilator RTL simulator, cocotb design verification and several
others.

Zvonimir Z. Bandić is the Research Staff Member and Senior Director of
Next Generation Platform Technologies Department in a Western Digital
Corporation in San Jose, California. He received his BS in electrical
engineering in 1994 from the University of Belgrade, Yugoslavia, and his
MS (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in
the field of novel electronic devices based on wide bandgap
semiconductors. He is currently focusing on emerging Non-Volatile
Memories (PCM, ReRAM, MRAM) applications for data center distributed
computing, including RISC-V based CPU technologies , in-memory compute,
RDMA networking, and machine learning hardware acceleration. He has been
awarded over 50 patents in the fields of solid state electronics, solid
state disk controller technology, security architecture and storage
systems and has published over 50 peer-reviewed papers. Zvonimir is
Chairman of CHIPS Alliance, Chair of OpenCAPI org, and Board of
Directors member of RISC-V standards organization.

*Open Source Hardware meets Open Source Software*
George Grey, @gcgrey

The RISC-V architecture spans 32 bit micro-controllers to 128 bit
advanced multi-core SoCs. The free and open ISA encourages and
accelerates innovation and differentiation in hardware design. However,
a large part of the cost of ISA support is the delivery and evolution of
a software ecosystem. Software fragmentation has historically been a
significant industry challenge. This is particularly true in the IoT,
embedded and Edge device markets, where there is an unlimited range of
different hardware configurations and use cases. This talk will discuss
different paths to development of the RISC-V software ecosystem in a
world where billions of devices are now being connected, requiring
universal standards for IoT to Cloud end to end applications, including
security and over the air updates for every device.
George is CEO of Foundries.io. He was previously CEO of Linaro Ltd,
leading open source software collaboration in the Arm ecosystem for the
last 8 years. Prior to joining Linaro, George led software and hardware
technology companies for over 25 years, gaining wide ranging expertise
in business strategy, product development, sales and marketing. He has
built a reputation for leading and growing technology companies, and
brings extensive experience in creating innovative products and
solutions for global markets to Foundries.io. George holds a degree in
Electrical Sciences from Cambridge University and currently resides in
Cambridge, UK.

*Ripes: Teaching computer architecture through visualization*
Morten Borup Petersen

The presentation will provide an overview of typical topics covered in
an introductory computer architecture course to motivate the use of
visual tools in teaching.

We will then take a look at Ripes, an application for visually
simulating a 5-stage pipeline implementing the RISC-V instruction set.

Besides simulation, the main purpose of Ripes is to visualize the
implications of control- and data hazards on the processor
microarchitecture.

Find the source code for Ripes at: https://github.com/mortbopet/Ripes

Morten is at the EPFL, Switzerland, specializing in computer engineering
and embedded systems. He is the author of Ripes, an open-source
application for teaching computer architecture through
visualization, using the RISC-V instruction set.  He has previously
interned at Arm Cambridge as well as published research on computer
architecture at the NorCAS and ARCS conferences.