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PXA270 ohci
Hi! all,
I was able to have OHCI of PXA270 work on GUMSTIX.
The drivers/usb/host/ohci-pxa27x.c of Linux was referred to by this work.
We have not initialized registers though they have initialized it in
pxa27x_start_hc() and pxa27x_ohci_select_pmm() for PXA270.
I think this process of the board dependence is more necessary for this
processing.
(* Ooops.. sorry, this tree is Linux MIPS (not ARM) ;-)
http://www.linux-mips.org/git?p=linux.git;a=blob;f=drivers/usb/host/ohci-pxa27x.c;h=e44dc2cbca24006e1b81d57cf589213ee823295c;hb=HEAD
However, Linux initializes ohci registers of zaurus. Next, Linux boots
NetBSD/zaurus. Then, there is a possibility that this processing becomes
obstructive.
How should we mount these processing?
Moreover, pxaudc sets GPIO that depends on the board. For instance, my
GUMSTIX is unnecessary such a setting.
To begin with, do you know for whom this setting is setting?
Thanks,
--
kiyohara
Index: sys/arch/arm/xscale/pxa2x0_ohci.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0_ohci.c,v
retrieving revision 1.3
diff -u -r1.3 pxa2x0_ohci.c
--- sys/arch/arm/xscale/pxa2x0_ohci.c 4 Apr 2008 17:44:43 -0000 1.3
+++ sys/arch/arm/xscale/pxa2x0_ohci.c 23 Jan 2009 14:20:51 -0000
@@ -67,6 +70,7 @@
{
struct pxaohci_softc *sc = device_private(self);
struct pxaip_attach_args *pxa = aux;
+ bus_space_handle_t powman_ioh;
usbd_status r;
const char *devname = device_xname(self);
@@ -100,6 +104,18 @@
pxa2x0_clkman_config(CKEN_USBHC, 1);
pxaohci_enable(sc);
+ /* Clear any OTG Pin Hold, if asserted. */
+ if (bus_space_map(sc->sc.iot, PXA2X0_POWMAN_BASE, PXA2X0_POWMAN_SIZE,
+ 0, &powman_ioh) != 0) {
+ aprint_error(": couldn't map POWMAN memory space\n");
+ return;
+ }
+ if (bus_space_read_4(sc->sc.iot, powman_ioh, POWMAN_PSSR) &
+ POWMAN_OTGPH)
+ bus_space_write_4(sc->sc.iot, powman_ioh, POWMAN_PSSR,
+ POWMAN_OTGPH);
+ bus_space_unmap(sc->sc.iot, powman_ioh, PXA2X0_POWMAN_SIZE);
+
/* Disable interrupts, so we don't get any spurious ones. */
bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
OHCI_MIE);
@@ -233,7 +249,29 @@
hr = HREAD4(sc, USBHC_HR);
HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE));
hr = HREAD4(sc, USBHC_HR);
- HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSEP2));
+ HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) &
+ ~(USBHC_HR_SSEP1 | USBHC_HR_SSEP2 | USBHC_HR_SSEP3));
+ HWRITE4(sc, USBHC_HIE, USBHC_HIE_RWIE | USBHC_HIE_UPRIE);
+
+ hr = HREAD4(sc, USBHC_UHCRHDA);
+/*
+ * XXXXX:
+ * Check inf->port_mode of your machine.
+ * see 'struct pxaohci_platform_data' in linux-2.6.HOGE/arch/arm/mach-pxa/...
+ */
+#if 0 /* PMM_NPS_MODE */
+ HWRITE4(sc, USBHC_UHCRHDA, hr | UHCRHDA_NPS);
+#endif
+#if 0 /* PMM_GLOBAL_MODE */
+ HWRITE4(sc, USBHC_UHCRHDA, hr & ~(UHCRHDA_NPS | UHCRHDA_PSM));
+#endif
+#if 1 /* PMM_PERPORT_MODE */
+ HWRITE4(sc, USBHC_UHCRHDA, (hr & ~UHCRHDA_NPS) | UHCRHDA_PSM);
+
+ hr = HREAD4(sc, USBHC_UHCRHDB);
+ HWRITE4(sc, USBHC_UHCRHDB,
+ hr | UHCRHDB_PPCM(1) | UHCRHDB_PPCM(2) | UHCRHDB_PPCM(3));
+#endif
}
static void
Index: sys/arch/arm/xscale/pxa2x0reg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0reg.h,v
retrieving revision 1.17
diff -u -r1.17 pxa2x0reg.h
--- sys/arch/arm/xscale/pxa2x0reg.h 17 Oct 2007 19:53:45 -0000 1.17
+++ sys/arch/arm/xscale/pxa2x0reg.h 23 Jan 2009 14:20:52 -0000
@@ -973,6 +973,8 @@
#define UHCRHDA_PSM (1<<8) /* Power switching mode */
#define UHCRHDA_NDP_MASK 0xff /* Number downstream ports */
#define USBHC_UHCRHDB 0x004c /* UHC Root Hub Descriptor B */
+#define UHCRHDB_PPCM(p) ((1<<(p))<<16) /* Port Power Control Mask
[1:3] */
+#define UHCRHDB_DNR(p) ((1<<(p))<<0) /* Device Not Removable [1:3] */
#define USBHC_UHCRHS 0x0050 /* UHC Root Hub Stauts */
#define USBHC_UHCHR 0x0064 /* UHC Reset Register */
#define UHCHR_SSEP3 (1<<11) /* Sleep standby enable for port3 */
@@ -1059,4 +1061,119 @@
#define SSSR_RNE (1<<3)
#define SSP_SSDR 0x10
+/*
+ * Power Manager
+ */
+#define POWMAN_PMCR 0x00 /* Power Manager Control Register */
+#define POWMAN_BIDAE (1<<0) /* Imprecise-Data Abort Enable for nBATT_FAULT*/
+#define POWMAN_BIDAS (1<<1) /* Imprecise-Data Abort Status for nBATT_FAULT*/
+#define POWMAN_VIDAE (1<<2) /* Imprecise-Data Abort Enable for nVDD_FAULT */
+#define POWMAN_VIDAS (1<<3) /* Imprecise-Data Abort Status for nVDD_FAULT */
+#define POWMAN_IAS (1<<4) /* Interrupt/Abort Select */
+#define POWMAN_INTRS (1<<5) /* Interrupt Status */
+#define POWMAN_PSSR 0x04 /* Power Manager Sleep Status Register */
+#define POWMAN_SSS (1<<0) /* Software Sleep Status */
+#define POWMAN_BFS (1<<1) /* Battery Fault Status */
+#define POWMAN_VFS (1<<2) /* VCC Fault Status */
+#define POWMAN_STS (1<<3) /* Standby Mode Status */
+#define POWMAN_PH (1<<4) /* Peripheral Control Hold */
+#define POWMAN_RDH (1<<5) /* Read Disable Hold */
+#define POWMAN_OTGPH (1<<6) /* OTG Peripheral Control Hold */
+#define POWMAN_PSPR 0x08 /* Power Manager Scratch-Pad Register */
+#define POWMAN_SP(n) (1<<(n)) /* Scratch Pad Register bit n */
+#define POWMAN_PWER 0x0c /* Power Manager Wake-Up Enable Register */
+#define POWMAN_WE(n) (1<<(n)) /* Wake-up Enable for GPIO<n>[0,1,3,4,9..15] */
+#define POWMAN_WEMUX2_38 (1<<16) /* Wake-up Enable for GPIO<38> */
+#define POWMAN_WEMUX2_53 (2<<16) /* Wake-up Enable for GPIO<53> */
+#define POWMAN_WEMUX2_40 (3<<16) /* Wake-up Enable for GPIO<40> */
+#define POWMAN_WEMUX2_36 (4<<16) /* Wake-up Enable for GPIO<36> */
+#define POWMAN_WEMUX3_31 (1<<19) /* Wake-up Enable for GPIO<31> */
+#define POWMAN_WEMUX3_113 (2<<19) /* Wake-up Enable for GPIO<113> */
+#define POWMAN_WEUSIM (1<<23) /* Wake-up Enable for Rise/Fall Edge from UDET*/
+#define POWMAN_WE35 (1<<24) /* Wake-up Enable for GPIO<35> */
+#define POWMAN_WBB (1<<25) /* Wake-up Enable for Rising Edge from MSL */
+#define POWMAN_WEUSBC (1<<26) /* Wake-up Enable for USB Client Port */
+#define POWMAN_WEUSBH1 (1<<27) /* Wake-up Enable for USB Host Port 1 */
+#define POWMAN_WEUSBH2 (1<<28) /* Wake-up Enable for USB Host Port 2 */
+#define POWMAN_WEP1 (1<<30) /* Wake-up Enable for PI */
+#define POWMAN_WERTC (1<<31) /* Wake-up Enable for RTC */
+#define POWMAN_PRER 0x10 /* Power Manager Rising-Edge Detect Enable */
+#define POWMAN_RE(n) (1<<(n)) /* Rising-Edge W-u GPIO<n> [0,1,3,4,9..15] */
+#define POWMAN_RE35 (1<<35) /* Rising-Edge W-u GPIO<35> */
+#define POWMAN_PFER 0x14 /* Power Manager Falling-Edge Detect Enable */
+#define POWMAN_FE(n) (1<<(n)) /* Falling-Edge W-u GPIO<n>[0,1,3,4,9..15] */
+#define POWMAN_FE35 (1<<35) /* Falling-Edge W-u GPIO<35> */
+#define POWMAN_PEDR 0x18 /* Power Manager Edge Detect Status Register */
+ /* Use bits definitions of POWMAN_PWER */
+#define POWMAN_PCFR 0x1c /* Power Manager General Configuration */
+#define POWMAN_OPDE (1<<0) /* 13MHz Processor Oscillator Power-Down Ena */
+#define POWMAN_FP (1<<1) /* Float PC Card Pins During Sleep/Deep-Sleep */
+#define POWMAN_FS (1<<2) /* Float Static Chip Selects (nCS<5:1>) Sleep */
+#define POWMAN_GPR_EN (1<<4) /* nRESET_GPIO Pin Enable */
+#define POWMAN_PI2C_EN (1<<6) /* Power Manager I2C Enable */
+#define POWMAN_DC_EN (1<<7) /* Sleep/Deep-Sleep DC-DC Converter Enable */
+#define POWMAN_FVC (1<<10) /* Frequency/Voltage Change */
+#define POWMAN_L1_EN (1<<11) /* Sleep/Deep-Sleep Linear Regulator Enable */
+#define POWMAN_GPROD (1<<12) /* GPIO nRESET_OUT Disable */
+#define POWMAN_PO (1<<14) /* PH Override */
+#define POWMAN_RO (1<<15) /* RDH Override */
+#define POWMAN_PGSR(x) (0x20+((x)<<2)) /* Power Manager GPIO Sleep-State */
+#define POWMAN_SS_REG(n) ((n)>>5) /* Register of Sleep State of GPIO<n> */
+#define POWMAN_SS_BIT(n) ((n)&0x1f) /* Bit of Sleep State of GPIO<n> */
+#define POWMAN_RCSR 0x30 /* Reset Controller Status Register */
+#define POWMAN_HWR (1<<0) /* Hardware/Power-On Reset */
+#define POWMAN_WDR (1<<1) /* Watchdog Reset */
+#define POWMAN_SMR (1<<2) /* Sleep-Exit Reset from Sleep/Deep-Sleep */
+#define POWMAN_GPR (1<<3) /* GPIO Reset */
+#define POWMAN_PSLR 0x34 /* Power Manager Sleep Configuration Register */
+#define POWMAN_SL_PI(x) ((x)<<2) /* PI Power Domain */
+#define POWMAN_SL_R0 (1<<8) /* Internal SRAM Bank 0 */
+#define POWMAN_SL_R1 (1<<9) /* Internal SRAM Bank 1 */
+#define POWMAN_SL_R2 (1<<10) /* Internal SRAM Bank 2 */
+#define POWMAN_SL_R3 (1<<11) /* Internal SRAM Bank 3 */
+#define POWMAN_SL_ROD (1<<20) /* Sleep/Deep-Sleep Mode nRESET_OUT Disable */
+#define POWMAN_IVF (1<<22) /* Ignore nVDD_FAULT in Sleep/Deep-Sleep Mode */
+#define POWMAN_PSSD (1<<23) /* Sleep-Mode Shorten Wake-up Delay Disable */
+#define POWMAN_PSTR 0x38 /* Power Manager Standby Configuration */
+ /* Use bits definitions of POWMAN_PSLR */
+#define POWMAN_PVCR 0x40 /* Power Manager Voltage Control Register */
+#define POWMAN_CMD_DELAY(n) ((n)<<7) /* Command Delay */
+#define POWMAN_READPTR(x) ((x)<<20) /* Read Pointer */
+#define POWMAN_VCSA (1<<14) /* Voltage-Change Sequencer Active */
+#define POWMAN_PUCR 0x4c /* Power Manager USIM Card Control/Status */
+#define POWMAN_EN_UDET (1<<0) /* Enable USIM Card Detect */
+#define POWMAN_USIM114 (1<<2) /* Allow UVS/UEN Functionality for
GPIO<114> */
+#define POWMAN_USIM115 (1<<3) /* Allow UVS/UEN Functionality for
GPIO<115> */
+#define POWMAN_UDETS (1<<5) /* USIM Detect Status */
+#define POWMAN_PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable */
+#define POWMAN_WE13 (1<<0)
+#define POWMAN_WE16 (1<<1)
+#define POWMAN_WE17 (1<<2)
+#define POWMAN_WE34 (1<<3)
+#define POWMAN_WE36 (1<<4)
+#define POWMAN_WE37 (1<<5)
+#define POWMAN_WE38 (1<<6)
+#define POWMAN_WE39 (1<<7)
+#define POWMAN_WE90 (1<<8)
+#define POWMAN_WE91 (1<<9)
+#define POWMAN_WE93 (1<<10)
+#define POWMAN_WE94 (1<<11)
+#define POWMAN_WE95 (1<<12)
+#define POWMAN_WE96 (1<<13)
+#define POWMAN_WE97 (1<<14)
+#define POWMAN_WE98 (1<<15)
+#define POWMAN_WE99 (1<<16)
+#define POWMAN_WE100 (1<<17)
+#define POWMAN_WE101 (1<<18)
+#define POWMAN_WE102 (1<<19)
+#define POWMAN_PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
+ /* Use bits definitions of POWMAN_PKWR */
+#define POWMAN_PCMD(x) (0x80+((x)<<2) /* Power Manager I2C Command Reg File */
+#define POWMAN_CD_MASK 0x0f /* I2C Command Data Mask */
+#define POWMAN_SQC_CNTINUE (0<<8) /* Sequence Configuration: Continue */
+#define POWMAN_SQC_PAUSE (1<<8) /* Sequence Configuration: Pause */
+#define POWMAN_LC (1<<10) /* Last Command */
+#define POWMAN_DCE (1<<11) /* Delay Command Execution */
+#define POWMAN_MBC (1<<12) /* Multi-Byte Command */
+
#endif /* _ARM_XSCALE_PXA2X0REG_H_ */
Index: sys/arch/arm/xscale/pxa2x0_udc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0_udc.c,v
retrieving revision 1.1
diff -u -r1.1 pxa2x0_udc.c
--- sys/arch/arm/xscale/pxa2x0_udc.c 17 Dec 2006 16:03:33 -0000 1.1
+++ sys/arch/arm/xscale/pxa2x0_udc.c 23 Jan 2009 14:20:51 -0000
@@ -80,17 +87,21 @@
bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_size,
BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
+#if 0 /* Maybe board independent. */
pxa2x0_gpio_set_function(35, GPIO_ALT_FN_2_IN); /* USB_P2_1 */
pxa2x0_gpio_set_function(37, GPIO_ALT_FN_1_OUT); /* USB_P2_8 */
pxa2x0_gpio_set_function(41, GPIO_ALT_FN_2_IN); /* USB_P2_7 */
pxa2x0_gpio_set_function(89, GPIO_ALT_FN_2_OUT); /* USBHPEN<1> */
pxa2x0_gpio_set_function(120, GPIO_ALT_FN_2_OUT); /* USBHPEN<2> */
+#endif
pxa2x0_clkman_config(CKEN_USBDC, 1);
pxaudc_enable(sc);
+#if 0 /* Maybe board independent... */
pxa2x0_gpio_set_bit(37); /* USB_P2_8 */
+#endif
sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname,
pxaudc_power, sc);
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