Re: NetBSD/vax vm for github testing

[Paul Koning <paulkoning%comcast.net@localhost>]

> On Jan 11, 2025, at 9:29 AM, John Klos <john%klos.com@localhost> wrote:
> 
>> I wrote multiprocessor support for NetBSD/vax many years ago; but not many vax machines can
>> have multiple CPUs. It did work on VAX8250, which was just over one VUPS (which is extremely
>> slow today). Also, emulating multiprocessor support in general using a multiprocessor
>> machine is extremely difficult, since you need to synchronise the CPUs so that they emulate
>> at exactly the same speed. -- Ragge
> 
> Just curious: why would multiple CPUs need to emulate at exactly the same speed? 

The question is how far you can deviate from the real hardware behavior before operating systems start to fail.  The answer is "it depends".  

Some MP systems have CPUs running at the same nominal speed but not phase-locked.  Others have them phase locked (CDC 6000 series mainframes, for example, since the whole assembly of processors runs from a single master clock).  A multi-threaded emulator can't reproduce that.

An OS is more likely to require some sort of partial order, and/or mutual exclusion, and/or time bounds on interactions among processors.  That may be doable, the trouble is to find out the bounds of "what can I get away with".  The other problem with that approach is that the answer will depend on the code that's running.  For example, a diagnostic might be more sensitive to small deviations than an OS, and if you have several OS the answers are likely to differ depending on which one  you're looking at.

Again, CDC mainframes provide a nice example.  It's possible to use multi-threading to emulate the two CPUs, but it isn't possible to have a thread per peripheral processor; the OS won't boot because the boot process has tight timing assumptions among multiple PPUs.  And even the standard emulator which is single-threaded and timeslices the various processors one or a few instructions at a time fails one of the diagnostics -- which is a strange one that depends on the timing of a slow CPU instruction vs. the timing of PPU instructions.

	paul