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Re: New Vax - future directions :-)

Den 2021-07-04 kl. 00:04, skrev Jason Thorpe:
On Jul 3, 2021, at 9:46 AM, Anders Magnusson <ragge%tethuvudet.se@localhost> wrote:

So, some thought about expanding the Vax architecture.

For userspace; the vax architecture itself leave the door open for expanding the word size.   The instructions are all defined to use only the part of a register it needs, so adding a bunch of 'Q' instructions are a no-brainer.  Argument reference will work as before.
The JMP/JSR/RET/... might need a Q counterpart, since it suddenly store/require 8 bytes instead of 4.
A PSL bit for “64-bit mode” would be fine, IMO.  It enables the 64-bit memory references in the control flow insns, and enables the Q-variant of the others.
Yep, thought of that, but I haven't come to any final conclusion yet.   This is something that can be thought of in the future. Compatibility mode for PDP11 did work well back then, so a mode bit for 64-bit would maybe be good as well.
Kernel; the hardware structures (SCB, PCB, ...) must all be expanded.  Memory management changed (but the existing leave much to wish for anyway).
All this is probably a quite simple update to the architecture.
Make the 64-bit mode work like the Alpha OSF/1 model, but define HW PTE bits for modified / referenced?  I mean, if you’re going to have them for traditional VAX VM, might as well have them for 64-bit mode.
The old VAX MM only have modified bit, not referenced, which has always been a problem. Anyway, in 64-bit mode the memory management could work in a totally different way than today.
I don't think it must be a 32-bit MM mode implemented.
IEEE floating point:
The current floating point formats are very like IEEE formats (compared to other pre-IEEE formats).  The F, G and H matches in layout the IEEE Single, Double and Extended but the exponent bias is slightly different and subnormal values are missing.
By adding the three IEEE formats I think it would require very few extra gates to make it behave like the DEC FP instead.
Save FPGA space by using a software-completion model like Alpha.
Yep, something like that.
Vax have had multiprocessor support since ~forever, but it may be a good idea to revise the interlock instructions.
There are only 7 of them and a few more would be nice.
Having it in a FPGA would make it simple to clone up many Vaxen in the same cheap chip :-)
For goodness sake, just add a compare-and-swap instruction!
I have been sketching how to make an efficient interlock mechanism to avoid overhead, and I think it can be implemented quite cheap.

Even though there are 288 instructions, a few are missing that would be nice.  For example;
- Unsigned mul/div.  Vax only have signed.
- logical shift right.  Vax have EXTZV, but it is an unneccessarily complicated instruction.
- AND.  Vax have BIC instead, but that (almost) always require a complement as well.
FWIW, Alpha has “and”, “or”, “xor”, and “andnot”, “ornot”, and “xornot”.
I think "and" was in the original vax specification but later removed by some reason.

-- Ragge

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