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Re: First new vax in ...30 years? :-)
Den 2021-07-03 kl. 19:56, skrev Paul Koning:
On Jul 3, 2021, at 6:14 AM, Anders Magnusson <ragge%tethuvudet.se@localhost> wrote:
some time ago I ended up in an architectural discussion (risc vs cisc etc...) and started to think about vax.
Even though the vax is considered the "ultimate cisc" I wondered if its cleanliness and nice instruction set still could be implemented efficient enough.
Well, the only way to know would be to try to implement it :-) I had an 15-year-old demo board with a small low-end FPGA (Xilinx XC3S400), so I just had to learn Verilog and try to implement something. And it just passed EVKAA.EXE:
EVKAA V10.4 Hardcore Instruction Test
Hit any key to continue
EVKAA V10.4 pass # 1(X) done!
EVKAA V10.4 pass # 19(X) done!
EVKAA V10.4 pass # 32(X) done!
EVKAA V10.4 pass # 4B(X) done!
EVKAA V10.4 pass # 64(X) done!
EVKAA V10.4 pass # 7D(X) done!
EVKAA V10.4 pass # 96(X) done!
EVKAA V10.4 pass # AF(X) done!
EVKAA V10.4 pass # C8(X) done!
EVKAA V10.4 pass # E1(X) done!^C
Having an emulation that can pass a serious instruction set diagnostic is a very impressive accomplishment, especially for an instruction set as complicated as the VAX. I suppose it helps a lot that it is very well documented, in particular in the VAX architecture standard.
Yep. And the instructions are very straight-forward, not much specialties.
I used the "Vax Architecture Reference Manual V6.1" from 1982 as reference.
Next step would be to be able to run EVKAB/C/D/E, but these test
programs require the diagnostic supervisor, so to be able to do that I
must emulate some architecture that DEC understands to be able to run it.
I'm slightly surprised myself. I only use about 6000 LUTs (logical
gates), and even though there is something that resembles microassembler
involved it's not much.
The fact that it fits into a "small low-end FPGA" is a nice demonstration of how much technology has advanced.
FPGA description: This FPGA has just over 1000 CLBs (Configurable
Logical Blocks), each with four slices. Each slice contains two LUTs +
some MUXes and sometimes a flipflop as well, ending up with about 9000
A LUT is the basic combinatorial building block in a FPGA, it has four
input and one output, and can be programmed to implement any function.
(it's actually a memory cell, 16x1 bit).
The next test is to confirm that it runs VMS. DEC large operating systems were traditionally used as final system test, since they stress the system beyond what diagnostics do.
Must implement the memory management stuff first, then try VMS :-)
I've been thinking about connecting the FPGA to a RPi, using Simh to
emulate the devices. Might be a fast way forward :-)
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