Re: Issues with compiler failures

[Paul Koning <paulkoning%comcast.net@localhost>]

> On Apr 1, 2019, at 6:06 AM, maya%netbsd.org@localhost wrote:
> 
> I accidentally came across the same failure while working on GCC.
> It's saying "we are seeing a pseudo-register in post-reload".
> 
> It's possible that the PSW needs to be considered a hard register, but I
> am not sure yet!

Not as PSW.  GCC does deal with condition codes, but they are implicit in the old (CC0) back end.  When you convert to CCmode, the condition code register is indeed a hard register.  That still isn't exactly PSW; there's more in PSW than just condition codes and those other bits aren't seen by GCC.

If you have an ISA with multiple condition code registers that would correspond to multiple GCC registers, probably hard registers, and they might not all have the same mode.  Consider pdp11, which has two: the condition bits in the PSW which GCC knows as a register of CCmode, and the similar bits in the FPU status which is a different register with a value in FCCmode.  VAX is easier with just one set of condition bits.

I've had some bugs like you're seeing; I'll try to remember what created them.

	paul