Re: VAX addressing modes

["Maciej W. Rozycki" <macro%linux-mips.org@localhost>]

On Thu, 10 Aug 2017, Johnny Billquist wrote:

> > The displacement used to calculate the new PC with BRB/BRW is a part of
> > the instruction itself, so it does go through the instruction fetch unit,
> > and consequently I$.  I think JMP (or for that matter MOVAx) PC-relative
> > deferred would be a better analogy.
> 
> I don't see the point of the argument.
> The casel instruction have a bunch of arguments, which is in the instruction
> flow, and is a part of the instruction. The disassembler should handle this
> correctly. It is absolutely broken to try and disassemble a part of the casel
> instruction as some other instruction.
> There are absolutely no problems to understand how many bytes actually are a
> part of the casel instruction, and that should be the end of it.

 Right, there are exactly three operands and they are handled correctly 
according to the addressing modes chosen, both in the assembler and the 
disassembler.  An assembly code example is actually given in the 
architecture standard[1], available online.

 That's no different from say ARM TBB and TBH instructions BTW.

References:

[1] "DEC Std 032 VAX Architecture Standard", Digital Equipment 
    Corporation, 15-Jan-1990, Doc Id: A-DS-EL00032-00-0 Rev J, p. 3-64

  Maciej