>> [...two-KA630 speculation...]
> The question, though, is how useful would it be.  The KA630 was
> designed to support a multiprocessor system, ***EXCEPT*** that the
> multiple processors do NOT share main memory.

They do if they want...with some restrictions.

It's not fully symmetric sharing; the processor that owns the memory
has to explicitly export it to the Qbus, and other processors pay a
speed penalty (because they access it via Qbus cycles rather than
through their own memory interconnect).

It's also limited by the address space of the Qbus, which as I recall
imposes a 22-bit (= 4MB) limit, which limit applies to the total amount
of memory exported by all processors.  And in practice the limit is
even less than that because you have to allow space for devices in that
4MB.

> They each have their own memory.

Yes.

> It will NOT support SMP or anything close.

I can't see why not.  There aren't very may respects in which they're
not symmetric:

- One CPU board also handles Qbus arbitration (in principle this is a
  separate device; it just happens to be on the same board as the CPU,
  disabled in all but the end CPU);

- One processor boots differently from the others (also true in all
  other MP systems I'm aware of, even supposedly-SMP systems);

- I think one processor has to handle all Qbus device interrupts, but
  it's been long enough I'm not sure of this.

Am I missing something?  I sure don't see anything there that makes it
incapable of symmetric multiprocessing.  Each CPU even has its own
console serial port, which a lot of supposedly-SMP systems don't.

It will not support a SMP OS which assumes that all processors have
equal access to all of RAM, but that's a disconnect between software
assumptions and reality, not anything inherently SMP-incapable.

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