I just wrote:

> So, in my opinion, today, it's *possible* for a skillful FPGA designer
> to craft a reimplementation of a pipelined VAX at about NVAX speeds
> (give or take a factor of two).  You might be happier (and saner) ...

Sorry to reply to myself, but I cringed when I reread this.  The
"happier (and saner)" remark was only supposed to be a brief, humorous
way to convey my concerns about the challenging, perhaps mind-numbing,
complexity of implementing a pipelined VAX, fast, in an FPGA -- and
certainly not intended to insult or deride anyone or any idea!

I apologize for this poor choice of words (I am Canadian) and pray you
ignore them.

Thanks,
Jan Gray