It is possible to implement 100-150 MHz (and faster) pipelined RISC
processors in small fractions of modern FPGAs (such as Xilinx
Virtex-II), in parts that cost well under $100.  In Virtex-II, a 32-bit
ALU has a latency under 4 ns, a dual ported 32-deep SRAM has a cycle
time around 3 ns, and the copious synchronous 18 Kbit dual ported block
RAMs have an access time, including sundry delays, of 4-5 ns.

I understand the NVAX was clocked down to about 11 ns cycle times.  So
you're in the same ballpark.

For boring random logic, designing with FPGAs is often like taking a
time machine back ten years.  Designs and techniques that made sense ten
years ago in full custom VLSI probably make sense (at about the same
speed and level of integration) in a modern FPGA.

On the other hand, if your design can be tailored to take good advantage
of the FPGA fabric, or of special features like the multiple embedded
PowerPC cores or the numerous 3 Gb/s serial links coming soon in
Virtex-II Pro, or if your system is in any event constrained by access
latency or pin bandwidth to external RAM or other resources, then
sometimes you can field a system that is competitive with the other
guy's full custom or ASIC solution.

So, in my opinion, today, it's *possible* for a skillful FPGA designer
to craft a reimplementation of a pipelined VAX at about NVAX speeds
(give or take a factor of two).  You might be happier (and saner)
building a chip multiprocessor of several simpler slower (non-pipelined,
microcoded) VAXes in a single FPGA.  Or you might simply host an
optimized port of SIMH in one or more of the PowerPCs in a Virtex-II
Pro.

Regarding the Sokolov piece, I don't see any advantage in using a third
party system controller when those functions are relatively easily
absorbed into an FPGA (relative to the staggering complexity of a
pipelined implementation of the CISCy VAX instruction set architecture).

Whether or not Mr. Sokolov achieves his goal, I can assure you that
building and booting your own processors and systems, from the gates up,
is both educational and quite a lot of fun, and I look forward to
reading about his progress.

Jan Gray, Gray Research LLC
FPGA CPU News: www.fpgacpu.org