At 09:05 PM 6/26/01 +0100, Matt London wrote:

>$200 (even AU$) is a lot for me - I'm a poor student :&)
>
>However, as a project, it'd be great fun I suspect. I'd be more than happy
>to join in :&)
>
>Any takers?


Well, the WebPACK ISE tools are a free download from Xilinx (you can also 
call the local sales rep for Xilinx whoever that is in your area and get 
them on a mini-CD)

Next if you get access to the 780 prints I can probably teach enough VHDL 
to start doing a gate level implementation. Basically this would involve 
doing some simple VHDL equivalents of TTL gates and then wiring them 
together just like they are in the schematics. I'm guessing we'd use some 
fast static RAM for the WCS and no doubt you would want to load it 
remotely. Then its just a matter of
         typing
         simulating
         fixing
Until the model works just like the real thing. Cost is $0 (other than 
time) until you actually want to start downloading it.

And yes the gate level version would be inefficient however as the test bed 
for a RTL specified one it would be invaluable.

--Chuck