On Thu, 31 May 2001, Brian Chase wrote:

> On Thu, 31 May 2001, Stephen Bell wrote:

> > On Tue, 29 May 2001, Carlini, Antonio wrote:
> 
> > > The VS3100/uV3100 options connect to an
> > > option connector on the mainboard. This more or
> > > less exposes the CDAL bus to you. My memory
> > > does not go much further than this but I can
> > > see if I still have the relevant details
> > > kicking around anywhere if you like.
> > >
> > > If you were designing your own I/O card
> > > this is where you would connect.
> 
> >    If you can find the details, that would be excellent!!
> 
> I hadn't thought about the option cards.  Even if it isn't possible to
> directly interface to the CDAL bus (for lack of documentation or
> whatever), one might be able to take Stephen's idea and hijack access to
> the video RAM on one of the framebuffer option cards or even to the RAM
> of the onboard monochrome framebuffer.
> 
> -brian.

Hi, 
   I had thought about pluging into system ram slots, but there's a few 
   problems with that.. video RAM is a pretty darn good idea though.   

   I've got a few things to checkout on the prom side & will look into
   the framebuffer ram as well.

Cheers,
   Steve.

P.S
   2.5 x PDP-11/44 w/SCSI rescue mission now underway.. (ROLL ON DUNGEON, YEAH) 

P.P.S
   vaxen looken report from last night:
   Cracked open a few boxes to have a look at things, 
   I had always thought the 2 3100 boxes I had were a vs3100/38
   & an mv3100/10e??, but now i'm not so sure. I may have at least one  
   southern hemisphere orphan or field upgraded system. 
   (quite a bit of wire wrap / reworking )

   Anyhow, the options connectors on these two look very different.
   One system has two NCR scsi controllers on the vax motherboard
   and routes the scsi signals up through the connector, basically
   the card looks like it's mostly just buffers/line drivers.

   The other options card has the SCSI & FDC controller
   chips plus what looks like an MVII cpu, this all looks pretty self 
   contained. I don't think this prom is any use,..
   
   Looks like going the connector route will require lots of DEC docs
   to support more than a handful of models

   The system eproms look tempting though, presumably these sit in 
   parallel as a single block of 16bit memory,,..

   things missing are...?? (and things I haven't looked into yet)
      - access to interrupts, hopefully vax interupts are, active
        low open collector types, which would make it easy to hook
        into something on the m/brd.
      - bus signals for "write" cycles, (easy for a "read not write" type 
        signal but would require separate routing for two separate async 
        signals )
      - possibility of needing to change data bus buffers if they 
        exist.(messy but easily enough done.)