Subject: Re: Status Vax 4000/60, 400/90, 4000/vlc
To: None <firstname.lastname@example.org, email@example.com>
From: None <firstname.lastname@example.org>
Date: 02/23/2000 02:59:01
>Think, it's because of the missing cache. I tried again some days ago, but i
>don't get this cache running. It's different from KA660 cache enabling. But the
>box runs fine, just a bit slow, and SCSI is missing on all 4000s (NCR5394).
I've just (quickly) compared the KA48 and KA660 docs and there do seem to be
some slight differences. The most obvious one is that the VLC only has a
primary cache and no backup cache; so none of the registers associated with the
backup cache exist.
This is a sumamry of the cache, NI and SCSI info. I assume that there is enough
public information kicking around about LANCE and NCR 53C94. If there isn't
then you'll have a hard time since all the docs I've seen mainly refer to the
manufacturer's docs for these.
Cache Control Register (CCR) (IPR 25 hex, 37 decimal)
bit 3: Compare Wrong Parity - used for diags, should be clear
bit 2: Enable cache - set to enable, clear to disable
bit 1: Flush cache - write only bit; writing a 1 will flush the cache
bit 0: Diag mode. When set allows access to the cache via some part
of memory space (same as the KA655 I guess).
BEHR access is described below.
Cache data lines are accessible as 20150400-201507FF
Cache tags are accessible as 20150000-201503FF
Cache data lines:
When cache diag mode is set, accesses to data lines (see above)
will write to the line indexed by bits 9:2 of the address and
lines will be written for all enabled banks.
Reads return data from the highest priority enabled bank.
0 is the highest priority bank
Cache tag lines:
When cache diag mode is set, accesses to tags (see above)
will write to the tag indexed by bits 9:3 of the address and
tags will be written for all enabled banks.
31: tag parity
30: valid bit
Reads also return data parity for the accessed address in bits 3:0
Bank Enable Hit Miss Reg (BEHR)
Longword access only. Accessed via any longword address in the
range 20150800:2015FFFF when the CCR diag bit is set.
bits 15:8 are read only and indicate that the latest D stream
read or write hit in a particular bank
bits 7:0 are the bank enables for the various banks. Now any given SOC
may not have all banks functional. Broken banks are permanently
disabled during chip manufacture.
The correct procedure to enable the primary cache is:
Write 1 to Cache Control diagnostic bit (bit 0)
Write 0xFF to the BEHR to enable all banks
Write all tags with V=0 and correct parity.
Write a 1 to the Cache Control flush cache bit (bit 1).
Disable cache diagnostic mode
The ethernet is LANCE-based.
NI_RDP is at 200E0000
NI_RAP is at 200E0004
The SCSI controller is a 53C94. The chip's internal registers are
accessible as 13 longwords starting from 200C0000.