<  An MSCP controller would require quite a bit of hacking, and some process
<power on the board.  MSCP is a rather complex protocol along the same lines
<SCSI, but we don't have fancy MSCP chips around like SCSI does in the 53C9
<vein and such.

It would be impossible to reduce MSCP to a chip as it's a high level logical 
protocal and would require a LOT of smarts (aka 2900, DEC T11 or 80186)
to translate that to the device.

<sometimes an Am2910 microsequencer.  It could, I suppose, be done nowadays
<with a PIC microcontroller or something like that.  But it would definitel
<take some doing.

PIC lacks the ram and likely enough rom too.  Look at RQDXn T11 cpu and
at least 8Kwords of rom plus at least 2kw of ram for buffers.

<  Speaking of fun projects and Xilinx chips...I'd *love* to have an FPGA
<implementation of a pdp8 (probably an 8/e) with an IDE interface. :-)

IDE for PIO is something that would fit in a low end Xilinx FPGA.  The 
only problem is PIO is SLOW though cheap on interface logic.

The PDP8 would barely require that.  I've looked at it and if you dont mind 
tossing 4bits out of every 16 (IDE data transfer is 16bits wide) it's pretty 
trivial Omnibus hack.  If your cheap about wasting bits you can pack two 
12bit words to three bytes but then a bit more smarts are needed to buffer 
the transfer.

Allison