Hi !

> The KA660 interval timer (ICCS), IPR 0x18, is implemented according to the
> interval clock control/status register (ICCS), is implemented as the
> standard subset of the Standard VAX ICCS in the CPU chip; while NICR and ICR
> are not implemented.  Figure 7-2 shows the format and table 7-1 describes
> the bits.

Ok, this makes the thing a bit more strange, but as i see, this might not
be a big problem. As i remember, we need exactly 10 ms, so it fits out
needs.
I'll try to modify the booter this weekend.

so long.. Michael