Subject: RE: I have the KA660 tech manual
To: Michael Kukat <michael@camaronet.de>
From: Lindgren, Jon <jlindgren@espus.com>
List: port-vax
Date: 06/24/1999 07:56:02
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> Fine, this helps very much for the 4000 series.
>
> Another thing i must know for this very strange CPU:
> As i see, the SOC CPU is a big bunch of strange design by
> DEC. For several decades, every VAX had a processor register
> called NICR, the next interval clock register. This is the
> base for the new booter counting correctly on every box...
> except my VAXstation 4000 VLC. Now i did the usual:
>
> [snip]
Correct - register 19 is not implemented, according to the TM. Register
0x18 is the ICCR, however, which from what I understand, will suffice. From
section 7 of the TM:
--------------[begin plagiarism]----------------
7.2 - Interval Timer (ICCS) - EPR 0x18
The KA660 interval timer (ICCS), IPR 0x18, is implemented according to the
interval clock control/status register (ICCS), is implemented as the
standard subset of the Standard VAX ICCS in the CPU chip; while NICR and ICR
are not implemented. Figure 7-2 shows the format and table 7-1 describes
the bits.
31 7 6 5 0
______________________ _ ________
|_________MBZ__________|_|__MBZ___|
Figure 7-2 - Interval Timer (ICCS) (EPR 0x18)
Bit Name Description
--------------------------------------------------------------------------
<31:7> MBZ Read as zero. Must be written as zero.
<6> IE Interrupt enable. Read/write. This bit enables and
disables the interval timer interrupts. When the bit
is set, and interval timer interrupt is requested
every 10 msec with an error of less than 0.01%. When
the bit is clear, interval timer interrupts are
disabled. This bit is cleared on power-ip.
<5:0> MBZ Read as zero. Must be written as zero.
Table 7-1 Interval Timer Bit Descriptions
Interval timer requests are posted at IPL 16 with a vector of C0. The
interval timer is the highest priority device at this IPL.
---------------[end plagiarism]-----------------
> Cound you please try this also ? And please try "ex /i 19"
> also, i need those results. If you get similar error messages
> and no hex numbers, this is a SOC CPU problem. Then i need a
> bit of extract in the TM, if there exists some interval count
> register counting microseconds and generating interrupts on
> overflow or such stuff. This is very important for the
> kernel to work, because this is the only real working
> timebase it has. (I wonder how my kernel ever could work
> on the VS 4000 VLC)
If you still need this stuff, let me know.
And of course, I'm working on getting out an html document with lots of info
for you.
-Jon Lindgren
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<TITLE>RE: I have the KA660 tech manual</TITLE>
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<BODY>
<P><FONT SIZE=3D2>> Fine, this helps very much for the 4000 =
series.</FONT>
<BR><FONT SIZE=3D2>> </FONT>
<BR><FONT SIZE=3D2>> Another thing i must know for this very strange =
CPU:</FONT>
<BR><FONT SIZE=3D2>> As i see, the SOC CPU is a big bunch of strange =
design by </FONT>
<BR><FONT SIZE=3D2>> DEC. For several decades, every VAX had a =
processor register</FONT>
<BR><FONT SIZE=3D2>> called NICR, the next interval clock register. =
This is the</FONT>
<BR><FONT SIZE=3D2>> base for the new booter counting correctly on =
every box...</FONT>
<BR><FONT SIZE=3D2>> except my VAXstation 4000 VLC. Now i did the =
usual:</FONT>
<BR><FONT SIZE=3D2>></FONT>
<BR><FONT SIZE=3D2>> [snip]</FONT>
</P>
<P><FONT SIZE=3D2>Correct - register 19 is not implemented, according =
to the TM. Register 0x18 is the ICCR, however, which from what I =
understand, will suffice. From section 7 of the TM:</FONT></P>
<P><FONT SIZE=3D2>--------------[begin =
plagiarism]----------------</FONT>
</P>
<P><FONT SIZE=3D2>7.2 - Interval Timer (ICCS) - EPR 0x18</FONT>
</P>
<P><FONT SIZE=3D2>The KA660 interval timer (ICCS), IPR 0x18, is =
implemented according to the interval clock control/status register =
(ICCS), is implemented as the standard subset of the Standard VAX ICCS =
in the CPU chip; while NICR and ICR are not implemented. Figure =
7-2 shows the format and table 7-1 describes the bits.</FONT></P>
<BR>
<P><FONT =
SIZE=3D2> 31 &=
nbsp; 7 6 =
5 0</FONT>
<BR><FONT SIZE=3D2> ______________________ _ ________</FONT>
<BR><FONT SIZE=3D2>|_________MBZ__________|_|__MBZ___|</FONT>
</P>
<P><FONT SIZE=3D2>Figure 7-2 - Interval Timer (ICCS) (EPR 0x18)</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>Bit =
Name Description</FONT>
<BR><FONT =
SIZE=3D2>---------------------------------------------------------------=
-----------</FONT>
<BR><FONT SIZE=3D2><31:7> =
MBZ Read as zero. Must =
be written as zero.</FONT>
<BR><FONT SIZE=3D2><6> =
IE Interrupt =
enable. Read/write. This bit enables and</FONT>
<BR><FONT =
SIZE=3D2> &nb=
sp; disables the =
interval timer interrupts. When the bit</FONT>
<BR><FONT =
SIZE=3D2> &nb=
sp; is set, and =
interval timer interrupt is requested</FONT>
<BR><FONT =
SIZE=3D2> &nb=
sp; every 10 msec =
with an error of less than 0.01%. When</FONT>
<BR><FONT =
SIZE=3D2> &nb=
sp; the bit is =
clear, interval timer interrupts are</FONT>
<BR><FONT =
SIZE=3D2> &nb=
sp; =
disabled. This bit is cleared on power-ip.</FONT>
<BR><FONT SIZE=3D2><5:0> =
MBZ Read as zero. Must =
be written as zero.</FONT>
</P>
<P><FONT SIZE=3D2>Table 7-1 Interval Timer Bit Descriptions</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>Interval timer requests are posted at IPL 16 with a =
vector of C0. The interval timer is the highest priority device =
at this IPL.</FONT></P>
<P><FONT SIZE=3D2>---------------[end =
plagiarism]-----------------</FONT>
</P>
<P><FONT SIZE=3D2>> Cound you please try this also ? And please try =
"ex /i 19" </FONT>
<BR><FONT SIZE=3D2>> also, i need those results. If you get similar =
error messages</FONT>
<BR><FONT SIZE=3D2>> and no hex numbers, this is a SOC CPU problem. =
Then i need a</FONT>
<BR><FONT SIZE=3D2>> bit of extract in the TM, if there exists some =
interval count</FONT>
<BR><FONT SIZE=3D2>> register counting microseconds and generating =
interrupts on</FONT>
<BR><FONT SIZE=3D2>> overflow or such stuff. This is very important =
for the</FONT>
<BR><FONT SIZE=3D2>> kernel to work, because this is the only real =
working </FONT>
<BR><FONT SIZE=3D2>> timebase it has. (I wonder how my kernel ever =
could work</FONT>
<BR><FONT SIZE=3D2>> on the VS 4000 VLC)</FONT>
</P>
<P><FONT SIZE=3D2>If you still need this stuff, let me know.</FONT>
</P>
<P><FONT SIZE=3D2>And of course, I'm working on getting out an html =
document with lots of info for you.</FONT>
</P>
<P><FONT SIZE=3D2>-Jon Lindgren</FONT>
</P>
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