On Sun, 21 Feb 1999, Brian D Chase wrote:
>>   But...I want to remind folks that, just in case anyone has forgotten,
>> that this is about as far from an accurate measure of system performance
>> as one can get.  Good rc5 performance depends on certain instructions
>> (rotates, if I recall correctly) being supported by the processor in
>> question.  Very few processors have these instructions, Intel's and
>> PowerPC being the only two common ones that I'm aware of.  VAXen do not
>> (also if I recall correctly). 
>
>Oh come now, even if you had no idea if it existed, postulating that the
>VAX architecture would be missing any instruction `XYZ' is like playing
>Russian roulette with five bullets instead of one.  :-)

  Too true. ;)

>Opcode 9C, ROTL - rotate long.  There are also shift instructions for 32
>and 64bit operands: ASHL and ASHQ.  I'd guess that with some hand
>optimized assembler we'd see better performance.  God only knows what
>other VAX instructions could be used or abused into speeding up things. 

  Like I said, "if I recall correctly"...I obviously didn't. :)

>Of course, performance will also depend on how the instructions are
>microcoded.  Since the shifts and rotates are given 1 byte opcodes, I'm
>guessing they were judged as more likely to be used than some of the
>extended data instructions which used 2 byte opcodes.  Still, I don't
>having any timing info on the different instructions for the different VAX
>models.

  Any VAX Macro gurus out there feel like writing an rc5 core?


  Since this has come up before, here's the info on which my statement was
based, from distributed.net's rc5 faq:

> Why are Intel and PowerPC computers so much faster than other
> platforms?
>
>   Integral to the mathematics of the RC5 algorithm are 32-bit rotate
> operations. For whatever reason, the designers of the x86 and the
> PowerPC architectures decided to implement the rotate function as a
> hardware instruction. Many other CPUs do not have built-in hardware
> rotate instructions and must emulate the operation by (at the very
> least) two shifts and a logical OR. This handicap is why many
> non-Intel and non-PowerPC computers run RC5 slower than one might
> expect based on real-world benchmarks. It is also the main reason why
> the RC5 client is a poor benchmark to use in determining the speed or
> performance of a particular CPU.


                    -Dave McGuire