Subject: Re: Setting up a T1 and email
To: John Wilson <email@example.com>
From: Sheila //or// Bob (depends on who's writing) <firstname.lastname@example.org>
Date: 07/16/1998 17:53:26
John Wilson wrote:
> >From: Dave McGuire <email@example.com>
> > Which is exactly why, in the VAX/PDP world, the DH11 series serial muxes were
> >designed. On my 11/34a I had a DH11-AD, which was 16 serial ports with full
> >modem control that DMA'd incoming characters into buffers in memory, not
> >bothering the host CPU. It was very, VERY nice...especially since it replaced
> >an interrupt-per-character DZ11. :)
> Actually, reception works pretty much identically between the DH11 and DZ11,
> they both tag incoming characters with their line number and stick them into
> a unified FIFO which the CPU sucks out on interrupts (the DH11 gets to set
> the FIFO alarm level though). Transmission is where the big difference is,
> the DH11 can send a whole buffer via DMA with just one interrupt at the end,
> and the DZ ints after each character goes out.
> DMA input sounds like a great idea but it would add a lot of complexity, in
> regular (cooked) mode the CPU will just grab each character right back out
> of memory one at a time anyway to decide whether it does anything special,
> and then on the rare occasions when you get to do full bore binary input it
> will need basically a whole second version of the receive handler that just
> packs up a buffer at a time at a time and ships it in.
> John Wilson
> D Bit
however, the comm iop did provide a path for off loading the cpu for
handling DU, DUP, and/or DZ interrupts!! Simple little single board
harvard architecture machine with a 180NS cycle time.
real address is shsrms at erols dot com
The Herbal Gypsy and the Tinker.