<I don't know...  If on some of the CVAX processors the on-chip 1k cache i
<at 90ns, DRAM might not be entirely unreasonable.  DRAM rated at 120ns wa
<common around '87 and '88, and I'm sure some exotic 100ns chips may have
<been around somewhere too. :-)

Actually 100ns parts were common and 80ns were findable... but the spec 
is deceiving.  You still have to supply ras/, cas/ and then the 80ns spec 
is valid...the multiplexed address can easily add 20-40ns not counting 
surrounding logic.  In a system memory speeds for Drams are a piece of 
the total picture.  For static ram generally that is a different case 
and even in '81 you could get 2147 (50ns 1kx4) and 2167 (45ns 16kx1).
Back then 200ns drams were common but, the memory system complete would 
be in the range of 240ns or more and there is also a cycle time for those 
that is ~350ns.  Cycle time is the total time to complete one read or 
write cycle and is often longer than access time, this tends to be a Dram
specific (and some static rams with dynamic logic) characteristic.

So that means the 1k cache can be hit every 90ns for data where the bigger 
dram cache (assuming 80ns) or main memory parts would only allow IO every 
120-140ns min. Of course with cache you can do something that drams can do 
fast and thats initiate a page read cycle where each successive location 
on requires a partial access cycle.  If you have a cache it works as you 
get a cache miss and page read the required data from the larger Dram 
array into the cache.  Also while you may be executing complex 
instructions you can be page reading the next block of instructions. There 
are other tricks that can be used to take advanatge of page mode to get 
the data faster.  But there are limits.


Allison