<According to my uVAX 3600 tech-info (EK-O35AA-IS-001) user manual 
<(which is a CVAX AFAIK) it has:
<
<	1 Kbyte on-chip cache @90 ns.
<	64 Kbyte second-level cache @180 ns.
<
<Or did you mean something else?

Hummm, I could be wrong but I'd been told (in 1989 when I was involved in 
doing the LPS20/32 program) that the Cvax chip was cacheless.  I had no 
docs to confirm it.  Oops, wrong on that one.

However for that chip the second level cache at 180ns is not fast and 
likely to get around something slower like qbus accesses as the PMI 
memory ran about that speed as well.


Allison