>From: der Mouse  <mouse@Rodents.Montreal.QC.CA>

>I have worked with a MicroVAX-II system with two CPUs in a single
>backplane.  It was the backplane with three C/D slots; I can never
>remember the nomenclature.  We had a KA630 in slot 1, a memory board in
>slot 2, and another KA (I think it was a 630 at one point and a 620 at
>another) in slot 3.  The slave processor had only its onboard 1M of
>memory, of course, but it didn't break anything to have it plugged into
>the same C/D interconnect as the master CPU and the memory board.
>
>No backplane hacks were required; it was a stock bus.

I'm probably about to show my ignorance but -- why isn't it OK for the 2nd
CPU to have memory boards too?  My understanding of the BA(1)23 Q/CD slots
is that on the CD half, the pins on side 1 of one slot are connected to the
corresponding pins on side 2 of the next slot over, i.e. each slot can only
see its immediate neighbors because the CD slots aren't bussed.  Right?
Looking at the KA630/MS630 boards seems to support this;  the KA630 only
really uses one side of the CD slots (the other side has only a couple of
connections that just look like power/ground or something), and the MS630
appears to pass most of the CD signals through from one side to the other.
If that's correct, then the KA630 can only feed the string of MS630s in
later slots, if there's another KA630+MS630(s) earlier in the backplane it
shouldn't matter (to the memory system anyway) since the KA630 doesn't even
have edge fingers on that side.

Right?  I don't know how the KA630 maps Q-bus DMA to VAX memory but hopefully
there's a way to disable pages, so that you don't have both KA630s responding
to the same DMA request.  A bit of real Q-bus memory would be an easy but
ugly way for the CPUs to communicate...

John Wilson
D Bit