>From: Arno Griffioen <arno@usn.nl>

>What I'm a bit worried about is the resulting speed from a PIO 
>design. What can we expect? VS3100 PIO speeds? 30 Kbyte/sec?

Note that IDE drives use a silo for I/O anyway (I think even in DMA mode) so
it's really not that bad.  It's just a matter of whether you want to add the
overhead of an instruction fetch for each word plus using separate cycles to
read the data word and write the memory (or the other way around) instead of
one combined DMA cycle.  Building the most obvious non-DMA non-MSCP IDE
controller would be very straightforward and I think the performance would
be quite usable.  If the machine's cache, main memory, and Q-bus bridge
overlap well enough, there might be surprisingly little performance difference
between a PIO and DMA controller.  Again the limiting factor is how long it
takes to do a Q-bus DATI/DATO cycle -- eliminating the DMA arbitration step
from each word might actually be a good thing (unless the plan was to use
block mode).

>How about a Qbus to PCI bridge ;-)

Bit3 makes one, model #615 (I have one here).  At $1600 it's probably not
the solution to the price/performance problems though!  And the PCI end can't
be a system controller so you'd need a PC to sit there and do configuration
and arbitration.  Seriously, building a lame PCI backplane that could have
DMA/interrupt access to a Q-bus might not be totally impossible, it just
seems like a bit much.

>For home-building DIP's are the way to go.. Definitely not SMD.. Bad
>for your nerves ;-)

But good for your knuckles!  :-)

John Wilson
D Bit