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Re: Pinouts for the P4 connector in 3/80, maybe others?

Le sam. 6 mai 2023 à 21:57, Jeremy Cooper <jeremy%baymoo.org@localhost> a écrit :
> Romain, I have been waiting nearly 25 years for someone to ask this question, apparently.

:-) good things come to those who wait! Thanks for keeping this
document for so long!

 > Here’s the little bit of reverse engineering I did of the P4 port
back in 1997.
> It’s not the full pinout, but it’s a start. I’ve never attached a PDF to this list before,
> so apologies if it doesn’t come through for the rest of you. I’ll gladly resent privately to anyone who asks.

The PDF came through, and is very useful thanks!
The signals you identified are a match (except for line and row
numbers being reversed, but that's a convention) for the ones in the
3/60 schematics.
Between that and the number of framebuffers that Izumi listed in the
FEH common for multiple systems, it seems the two are all but
Which will greatly help completing the pinouts - much easier to
validate what a pin is than trying to figure it out.

Do you remember how you checked the pins, was it just continuity
testing, follow traces, or something else?
I thought about continuity testing but I'm not sure how to do that
with no risk of damaging the boards... though that's more of a
question for an EE forum.

Thank you very much also Jeremy & Izumi for the pointers to NetBSD code!.

Now to also figure the signals from the 3/60 schematics - some are
obviously from the '030 (A[0-24], D[0-31], DSACK[0-1], SIZ[0-1, R/W,
all found by Jeremy, probably CLK?) but some are less obvious like
what is P4AS- and why is there two of them? V.INTY is probably some
form of VBL interrupt. INIT- could be reset? EN.VIDEO? DISACC (disable
acceleration ???)? C.S3? And I've yet to understand why there is a
semicolon and a number after some signals. Is that an internal
reference to somewhere else in the schematics or some signal
properties? Quite a bit more work to do as the schematics should
answer most of those questions :-)


Romain Dolbeau

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