SPARC hardware with weaker ordering than TSO

[Taylor R Campbell <riastradh%NetBSD.org@localhost>]

Does any actual hardware implement a weaker memory model than TSO?

I'm not asking whether you can technically set the bits in the
processor state field -- I'm asking whether the hardware will actually
reorder loads or stores or both in violation of the TSO rules, or the
PSO rules.

Also curious -- particularly for SPARCv7 or SPARCv8 -- what reordering
applies to I/O memory operations, since there's no MEMBAR #MemIssue
pre-v9.

References appreciated!