Re: fast softint support for sparc64

[David Laight <david%l8s.co.uk@localhost>]

On Sat, Jun 18, 2011 at 05:14:38AM +0900, Takeshi Nakayama wrote:
> >>> Eduardo Horvath <eeh%NetBSD.org@localhost> wrote
> 
> > If you're trying to order the store to the CI_MTX_COUNT with the store to 
> > L_CTXSWTCH then I think it should be #StoreStore.  
> > 
> > Note the comment in membar_ops.S:
> > 
> > /* These assume Total Store Order (TSO) */
> > 
> > Um, if you're running TSO then you don't need any membars at all.  We 
> > should really be coding this for RMO to get some performance improvements.  
> > Otherwise leaving them out will reduce instruction count and CPU cycles.
> 
> Ok, I will just leave it out.  Thank you for detailed comment.

Even assuming TSO, some of this code might require that the compiler not
re-order reads/writes (ie have memory locations cached in registers).

Writes to 'char' variables and marking variables 'volatile' does have this
effect, but has other overheads which may not be necessary.

I've used 'asm volatile("" ::: "memory")' [1] as a memory barrier to gcc.
The compiler has to assume that this 'instruction' might modify any
memory location - so cannot move loads/stores across it.

As well as helping synchronise things, it is also useful when gcc
generates code with a lot of temporary registers and end up spilling
them to stack instead of just writing the values to there targets.

        David

[1] Acually I use an asm comment including __LINE__ and an extra newline
to make the asm statement bigger!

-- 
David Laight: david%l8s.co.uk@localhost