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Re: SMP support for sparc64




Hmm, It seems I added some interrupt issue.  Can you provide the
dmesg log?  Can you see a traces if you break into DDB?

-- Takeshi Nakayama

I can't break into ddb, but after so some retesting, the error changed. Here is the dmesg log:

{6} ok boot disk Boot device: /sbus@3,0/SUNW,fas@3,8800000/sd@0,0 File and args: NetBSD IEEE 1275 Bootblock >> NetBSD/sparc64 OpenFirmware Boot, Revision 1.12 =0x857c28 Loading netbsd: 6764648+359400+523952 [507552+324810]=0x9a3508 xtlb[0]: Tag: 1000000 Data: e0000000ff000076 xtlb[1]: Tag: 1400000 Data: e0000000fec00076 xtlb[2]: Tag: 1800000 Data: e0000000fe800076 Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 The NetBSD Foundation, Inc. All rights reserved. Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. NetBSD 4.99.55 (GENERIC.MP) #1: Wed Mar 12 22:25:31 JST 2008 takeshi@nyx:/export/netbsd-cvs/src/sys/arch/sparc64/compile/GENERIC.MP total memory = 4096 MB avail memory = 3999 MB mainbus0 (root): SUNW,Ultra-Enterprise (8-slot Sun Enterprise E4500/E5500): hos9 cpu0 at mainbus0: SUNW,UltraSPARC-II @ 336 MHz, UPA id 6 cpu0: 32K instruction (32 b/l), 16K data (32 b/l), 4096K external (64 b/l) cpu1 at mainbus0: SUNW,UltraSPARC-II @ 336 MHz, UPA id 7 cpu1: 32K instruction (32 b/l), 16K data (32 b/l), 4096K external (64 b/l) central at mainbus0 not configured fhc at mainbus0 not configured sbus0 at mainbus0 addr 0xffdb6000: clock = 25 MHz DVMA map: ff800000 to ffffe000 IOTSB: 4324000 to 4326000 SUNW,socal at sbus0 slot 13 offset 0x10000 vector 22 ipl 2 not configured isp0 at sbus0 slot 1 offset 0x10000 vector 3 ipl 3 for QLGC,isp HSI at sbus0 slot 2 offset 0x20000 vector 4 ipl 6 not configured fhc at mainbus0 not configured timer0 at mainbus0 addr 0xffd99c00 sbus1 at mainbus0 addr 0xffd8e000: clock = 25 MHz DVMA map: ff800000 to ffffe000 IOTSB: 432c000 to 432e000 hme0 at sbus1 slot 3 offset 0x8c00000 vector 4 ipl 6: Sun Happy Meal Ethernet () hme0: Ethernet address XXXXXXXXXXXXXXXXXXXXXXXX nsphy0 at hme0 phy 1: DP83840 10/100 media interface, rev. 1 nsphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto esp0 at sbus1 slot 3 offset 0x8800000 vector 3 ipl 3: FAS366/HME, 40MHz, SCSI I7 scsibus0 at esp0: 16 targets, 8 luns per target timer1 at mainbus0 addr 0xffd7fc00 pcons0 at mainbus0 SMP kernel -- using %tick at 336MHz as system clock. scsibus0: waiting 2 seconds for devices to settle... scsibus1 at isp0: 16 targets, 8 luns per target scsibus1: waiting 2 seconds for devices to settle... Kernelized RAIDframe activated Fatal Reset 3,0>FATAL ERROR 3,0> At time of error: System software was running. 3,0> Diagnosis: Board 3, any system board MTIMEOUT (target of operation) 3,0>Log Date: Mar 12 21:44:17 GMT 2008 3,0> 3,0>RESET INFO for CPU/Memory board in slot 3 3,0> AC ESR 00000000.01000003 MTIMEOUT UPA_B_ERR UPA_A_ERR 3,0> DC[0] 00 3,0> DC[1] 00 3,0> DC[2] 00 3,0> DC[3] 00 3,0> DC[4] 00 3,0> DC[5] 00 3,0> DC[6] 00 3,0> DC[7] 00 3,0> FHC CSR 00050200 LOC_FATAL SYNC NOT_BRD_PRES 3,0> FHC RCSR 02000000 FATAL 3,0> Config policy change 3,0> 3,0>@(#) POST 3.9.30 2002/10/25 14:04 3,0>Copyright 2002 Sun Microsystems, Inc. All rights reserved. 3,0> SelfTest Initializing (Diag Level 10, ENV 0000ff01) IMPL 0011 MASK 20 3,0>Board 3 CPU FPROM Test 3,0>Board 3 Basic CPU Test 3,0> Set CPU UPA Config and Init SDB Data 3,0> SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0 3,0>Board 3 MMU Enable Test 3,0> DMMU Init 3,0> IMMU Init 3,0> Mapping Selftest Enabling MMUs 3,1>Board 3 CPU FPROM Test 3,1>Board 33BaEcachePU Test 3,0> Ecache Probe 3,1> Set CPU UPA Config and Init SDB Data 3,0> Ecache Tags 3,1> SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0 3,1>Board 3 MMU Enable Test 3,1> DMMU Init 3,1> IMMU Init 3,1> Mapping Selftest Enabling MMUs 3,1>Board 3 Ecache Test 3,1> Ecache Probe 3,1> Ecache Tags 3,0> Ecache Quick Verify 3,1> Ecache Quick Verify 3,0> Ecache Init 3,1> Ecache Init 3,0> Ecache RAM 3,1> Ecache RAM 3,0> Ecache Address Line 3,0> Configure Ecache Limit 3,0>Ecache Size = 00400000, Limited to 00400000 3,0>Board 3 FPU Functional Test 3,0> FPU Enable 3,0>Board 3 Board Master Select Test 3,0> Selecting a Board Master 3,1> Ecache Address Line 3,0>Board 3 FireHose Devices Test 3,1> Configure Ecache Limit 3,1>Ecache Size = 00400000, Limited to 00400000 3,1>Board 3 FPU Functional Test 3,1> FPU Enable 3,1>Board 3 Board Master Select Test 3,1> Selecting a Board Master 3,0>Board 3 Address Controller Test 3,0> AC Initialization 3,0> AC DTAG Init 3,0>Board 3 Dual Tags Test 3,0> AC DTAG Init 3,0>Board 3 FireHose Controller Test 3,0> FHC Initialization 3,0>Board 3 JTAG Test 3,0> Verify System Board Scan Ring 3,0>Board 3 Centerplane Test 3,0> Centerplane Join 3,0>Setting JTAG Master 3,0>Clear JTAG Master 3,0>Board 3 Setup Cache Size Test 3,0> Setting Up Cache Size 3,0>Board 3 System Master Select Test 3,0> Setting System Master 3,0>POST Master Selected (JTAG,CENTRAL) 3,0>Board 16 Clock Board Test 3,0> Clock Board Initialization 3,0> Clock Board Temperature Check 3,0>Board 16 Clock Board Serial Ports Test 3,0>Board 16 NVRAM Devices Test 3,0> M48T59 (TOD) Init 3,0>Board 3 System Board Probe Test 3,0> Probing all CPU/Memory BDA 3,0> Probing System Boards 3,0> Probing CPU Module JTAG Rings 3,0>Setting System Clock Frequency 3,0> CPU Module mid 6 Checked in OK (speed code = 7) 3,0> CPU mid 7 Version=00170011.20000507 3,0> CPU Module mid 7 Checked in OK (speed code = 7) 3,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336 3,0>TESTING BOARD 1 3,0>Board 1 JTAG Test 3,0> Verify System Board Scan Ring 3,0>Board 1 Centerplane Test 3,0> Centerplane Check 3,0>Board 1 Address Controller Test 3,0> AC Initialization 3,0>Setting Freq to 25MHZ 3,0> AC DTAG Init 3,0>Board 1 FireHose Controller Test 3,0> FHC Initialization 3,0>Board 1 NVRAM Devices Test 3,0> M48T59 (TOD) Init 3,0>Re-mapping to Local Device Space 3,0>Begin Central Space Serial Port access 3,0>Enable AC Control Parity 3,0>Hotplug Trigger Test 3,0>Init Counters for Hotplug 3,0>Board 3 Cross Calls Test 3,0>Board 3 Environmental Probe Test 3,0> Environmental Probe 3,0>Checking Power Supply Configuration 3,0>Power is more than adequate, load 2 ps 4 3,0>Reconfig memory due to FATAL RESET 3,0>Reconfig memory due to new CONFIG POLICY 3,0>Board 3 Probing Memory SIMMS Test 3,0> Probe SIMMID 3,0> Populated Memory Bank Status 3,0> bd # Size Address Way Status 3,0> 3 2048 Normal 3,0> 3 2048 Normal 3,0>Board 3 Memory Configuration Test 3,0> Memory Interleaving 3,0> Total banks with 8MB SIMMs = 0 3,0> Total banks with 32MB SIMMs = 0 3,0> Total banks with 128MB SIMMs = 0 3,0> Total banks with 256MB SIMMs = 2 3,0> Overall memory default speed = 60ns 3,0>Do OPTIMAL INTLV 3,0> Board 3 AC rev 5 RCTIME = 0 (Tras 71) 3,0> Board 3 AC rev 5 RCTIME = 0 (Tras 71) 3,0> Memory Refresh Enable 3,0>Board 3 SIMMs Test 3,0>TESTING IO BOARD 1 3,0>Board 1 I/O FPROM Test 3,0>@(#) iPOST 3.4.30 2002/10/25 14:03 3,0> TESTING IO BOARD 1 ASICs 3,0> TESTING SysIO Port 0 3,0>Board 1 SysIO Registers Test 3,0> SysIO Register Initialization 3,0> SysIO RAM Initialization 3,0>Board 1 SysIO Functional Test 3,0> Clear Interrupt Map and State Registers 3,0>Board 1 OnBoard IO Chipset (SOC) Test 3,0> TESTING SysIO Port 1 3,0>Board 1 SysIO Registers Test 3,0> SysIO Register Initialization 3,0> SysIO RAM Initialization 3,0>Board 1 SysIO Functional Test 3,0> Clear Interrupt Map and State Registers 3,0>Board 1 OnBoard IO Chipset (FEPS) Test 3,0>IO BOARD 1 TESTED 3,0>Probing for Disk System boards 3,0>Board 3 System Interrupts Test 3,0> 3,0> System Board Status 3,0>----------------------------------------------------------------- 3,0> Slot Board Status Board Type Failures 3,0>----------------------------------------------------------------- 3,0> 0 | Not installed | | 3,0> 1 | Normal |+IO Type 4 | 3,0> 2 | Not installed | | 3,0> 3 | Normal |+CPU/Memory | 3,0> 4 | Not installed | | 3,0> 5 | Not installed | | 3,0> 6 | Not installed | | 3,0> 7 | Not installed | | 3,0> 16 | Normal | Clock Board | 3,0>----------------------------------------------------------------- 3,0> 3,0> CPU Module Status 3,0>----------------------------------------------------------------- 3,0> MID OK Cache Speed Version 3,0>----------------------------------------------------------------- 3,0> 6 | y | 4096 | 336 | 00170011.20000507 3,0> 7 | y | 4096 | 336 | 00170011.20000507 3,0>----------------------------------------------------------------- 3,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336 3,0> Populated Memory Bank Status 3,0> bd # Size Address Way Status 3,0> 3 2048 0 2 Normal 3,0> 3 2048 1 2 Normal 3,0>
3,0>


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