On Sun, 26 Aug 2007, Martin Husemann wrote:

> On Sun, Aug 26, 2007 at 07:28:28PM +0200, Jochen Kunz wrote:
> > > And before you ask: we don't have support for Nevada cpus yet either.
> 
> [Side note: Niagara was the correct code name]
> 
> > Is this hard / time consuming? Or just a matter of "will come quick once
> > the SMP issues are ironed out"?
> 
> USIII(+) will probably come pretty soon.
> 
> I have no concrete ideas about Niagara, and don't have hardware myself.
> There are people who have the hardware, but I'd let them speak for themself.

Niagaras will probably need to be a separate port.  Since there's a HV
you can't access the MMU directly so you need a whole new pmap 
implementaton, and you're limited to 2 trap levels so all the trap 
entry/exit code and register window routines probably need to be 
rewritten.

> > Different TLB / pmap(4)?
> 
> USIII has some MMU extensions, the pmap will not be affected a lot. The
> machines use different PCI root bridges, but support for that is not too hard
> either (given that there is usable source code for them out there nowadays).

Don't forget the caches.  They are different enough that you probably 
can't get a stable system without changes there as well.

> > What about E[3456][05]00 support?
> 
> I don't know - do you have some spare machines?

The problem with those machines is the FHC backplane.  Not sure what
needs to be done for that.  You may be able to get away with a driver
that does nothing but match OBP nodes and assumes everything else is
transparent.  Or you may need to touch the hardware.

Eduardo