Subject: abbreviated instruction in delay slot
To: None <port-sparc64@netbsd.org>
From: Takeshi Nakayama <tn@catvmics.ne.jp>
List: port-sparc64
Date: 03/24/2003 19:31:31
Hello,

I found the problem described in subject from the 2nd chunk of this
OpenBSD's change.

	http://www.openbsd.org/cgi-bin/cvsweb/src/sys/arch/sparc64/sparc64/locore.s.diff?r1=1.29&r2=1.30

However, I think this change enbugged, since it breaks condition
register %g7.

So, I would like to commit the attached change in our tree.

Any comment?

Takeshi Nakayama

Index: locore.s
===================================================================
RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/locore.s,v
retrieving revision 1.172
diff -u -d -r1.172 locore.s
--- locore.s	2003/02/10 18:23:26	1.172
+++ locore.s	2003/03/24 08:43:45
@@ -2836,10 +2836,11 @@
 	CHKPT(%g2,%g5,0x16)
 
 	/* Did we save a user or kernel window ? */
-!	srax	%g3, 48, %g7				! User or kernel store? (TAG TARGET)
-	sllx	%g3, (64-13), %g7			! User or kernel store? (TAG ACCESS)
-	brnz,pt	%g7, 1f					! User fault -- save windows to pcb
-	 set	(2*NBPG)-8, %g7
+!	srax	%g3, 48, %g5				! User or kernel store? (TAG TARGET)
+	sllx	%g3, (64-13), %g5			! User or kernel store? (TAG ACCESS)
+	sethi	%hi((2*NBPG)-8), %g7
+	brnz,pt	%g5, 1f					! User fault -- save windows to pcb
+	 or	%g7, %lo((2*NBPG)-8), %g7
 
 	and	%g4, CWP, %g4				! %g4 = %cwp of trap
 	wrpr	%g4, 0, %cwp				! Kernel fault -- restore %cwp and force and trap to debugger