At 1:25 AM +0200 2002/05/02, de SAINT LEGER Rodolphe wrote:

>  qec0 at sbus0 slot 0 offset 0x20000 vector 4 ipl 2: 128K memory
>  qe0 at qec0 slot 0 offset 0x0 rev 1 address 08:00:20:86:a2:a0
>  qe1 at qec0 slot 1 offset 0x0 rev 1 address 08:00:20:86:a2:a0
>  qe2 at qec0 slot 2 offset 0x0 rev 1 address 08:00:20:86:a2:a0
>  qe at qec0 slot 3 offset 0x0 not configured

	Interesting.  Note that it disables qe3, whereas the U1 appears to bomb.

	Out of curiosity, can you build a 64-bit kernel (e.g., sparc64) 
for use on an SS5 (or similar machine), or does it use 32-bit (e.g., 
"sparc") kernels exclusively?

-- 
Brad Knowles, <brad.knowles@skynet.be>

"They that can give up essential liberty to obtain a little temporary
safety deserve neither liberty nor safety."
     -Benjamin Franklin, Historical Review of Pennsylvania.