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Re: SBus driver & burst (>32 bits) accesses

On Mon, 14 Dec 2020, Romain Dolbeau wrote:

> Hello,
> Writing a basic driver in NetBSD 9 for a SBus/FPGA board I've designed
> [1], I realized that all accesses to read or write my HW registers in
> the FPGA are done using 32 bits bus transactions, not burst mode
> (multiple 32 bits words in a single transaction). I've only
> implemented SBus 'slave' mode yet in the FPGA, and I'm using
> 'bus_space_write_8' in my driver - but the trace of my SBus Finite
> State Machine indicates transactions are still 32 bits (though maybe a
> bit faster than with 'bus_space_write_4', less overhead ?).
> For some reason, the onboard PROM is read with 8 bits accesses, but
> it's not a performance issue since it doesn't do anything beyond
> supplying the device name and register space.

That's because the firmware is presumabley FCode and is interpreted one 
byte at a time.

> Is there any way to speed up the access to write 128 bits at once with
> a 16-byte burst, or is there a hardware/software limitation? Do I need
> to implement 'master' mode and a DMA in the FPGA to get faster
> transfers?

I believe burst mode only works during DMA.

I assume you're on a SPARC here.

On SPARC the coherency space goes only as far as the external cache.  
Since the SBus space is uncached, the CPU will only do single bus 
transactions.  To use burst mode you will need to use DMA driven by the 
device and probably also need to make sure the IOMMU entries are set up to 
use the SBus controller's streaming cache.  This may only work on 
UltraSPARC machines since I don't think the SBus controllers on any of the 
32-bit SPARCs have streaming caches.


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